Short Form Data Sheet June 2012 MAX24305, MAX24310 5- or 10-Output Any-Rate Timing ICs with Internal EEPROM General Description Features Input Clocks The MAX24305 and MAX24310 are flexible, high- performance timing and clock synthesizer ICs that One Crystal Input include a DPLL and two independent APLLs. When Two Differential or CMOS/TTL Inputs locked to one of two input clock signals, the device performs any-to-any frequency conversion. From any Differential to 750MHz, CMOS/TTL to 125MHz input clock frequency 1Hz to 750MHz the device can Continuous Input Clock Quality Monitoring produce frequency-locked APLL output frequencies up Automatic or Manual Clock Selection to 750MHz and as many as 10 output clock signals that are integer divisors of the APLL frequencies. Input jitter Hitless Reference Switching on Loss of Input can be attenuated by an internal low-bandwidth DPLL. Low-Bandwidth DPLL The DPLL also provides truly hitless switching between input clocks and a high-resolution holdover capability. Programmable Bandwidth, 0.5mHz to 400Hz Input switching can be manual or automatic. Using only Attenuates Jitter up to Several UI a low-cost crystal or oscillator, the device can also serve as a frequency synthesizer IC. Output jitter is typically Free-Run or Holdover on Loss of All Inputs 0.35 to 0.5ps RMS (12kHz to 20MHz) on all outputs and Hitless Reference Switching on Loss of Input can be as low as 0.24ps RMS. Manual Phase Adjustment For telecom systems, the device has all required Two APLLs Plus 5 or 10 Output Clocks features and functions to serve as a central timing APLLs Perform High Resolution Fractional-N function or as a line card timing IC. With a suitable Clock Multiplication oscillator the device meets the requirements of Stratum 2, 3E, 3, 4E, and 4 G.812 Types I to IV G.813 and Any Output Frequency from <1Hz to 750MHz G.8262. Each Output Has an Independent Divider Output Jitter 0.35 to 0.5ps RMS Typical on All Outputs, Can Be As Low As 0.24ps RMS Applications Frequency Conversion and Synthesis Applications in a Outputs are CML or 2xCMOS, Can Interface to Wide Variety of Equipment Types LVDS, LVPECL, HSTL, SSTL and HCSL Telecom Timing Cards or Line Cards for SONET/SDH, CMOS Output Voltage from 1.5V to 3.3V Synchronous Ethernet and/or OTN General Features Suitable Line Card IC or Timing Card IC for Ordering Information Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU TEMP PIN- PART OUTPUTS Automatic Self-Configuration at Power-Up RANGE PACKAGE from Internal EEPROM Memory MAX24305EXG+ 5 -40 to +85 81-CSBGA Uses External Crystal, Oscillator or Clock MAX24310EXG+ 10 -40 to +85 81-CSBGA Signal As Master Clock +Denotes a lead(Pb)-free/RoHS-compliant package. Internal Compensation for Local Oscillator Frequency Error SPI Processor Interface 1.8V + 3.3V Operation (5V Tolerant) -40 C to +85 C Operating Temp. Range 10mm x 10mm CSBGA Package 1 Short Form Data Sheet MAX24305, MAX24310 1. Application Examples Figure 1-1. Telecom Timing Card 19.44M, OC1P/N 25M, etc. Primary and secondary IC1P/N OC2P/N clocks from clock OC3P/N IC2P/N OC4P/N selector FPGA OC5P/N System clocks to line cards OC6P/N 19.44M, 25M, etc. OC7P/N OC8P/N OC9P/N local MCP/N OC10P/N osc Figure 1-2. Synchronous Ethernet and SDH/SONET Line Card Synchronous Ethernet OC1P/N Clocks: any combination OC2P/N of 25M, 125M, 156.25M OC3P/N 19.44M, OC4P/N and related frequencies 25M, etc. From dual IC1P/N OC5P/N redundant Any combination of differential or IC2P/N timing functions 2x single-ended signal format OC6P/N OC7P/N OC8P/N SDH/SONET Clocks: OC9P/N Nx6.48MHz to 622.08MHz local MCP/N OC10P/N osc 2. Block Diagram Figure 2-1. Block Diagram DIV1 OC1POS/NEG DPLL APLL1 A Input Block DIV2 OC2POS/NEG Hitless Switching, 3.7-4.2GHz, Scaler, Divider, Jitter Filtering, Sub-ps jitter, DIV3 OC3POS/NEG Monitor Holdover Fractional-N B DIV4 OC4POS/NEG Figure 5-7 Figure 5-8 Figure 5-10 OC5POS/NEG DIV5 DIV6 OC6POS/NEG C APLL2 OC7POS/NEG DIV7 IC1POS/NEG 3.7-4.2GHz, IC2POS/NEG DIV8 OC8POS/NEG Sub-ps jitter, MCLKOSCP/N OC9POS/NEG DIV9 Fractional-N XIN D XO XOUT DIV10 OC10POS/NEG SPI Interface JTAG and HW Control and Status Pins 2 RST N TEST INTREQ GPIO1 GPIO2 AC / GPIO3 SS / GPIO4 CS N SCLK SDI SDO JTRST N JTMS JTCLK JTDI JTDO