Short Form Data Sheet April 2012 MAX24505, MAX24510 5 or 10 Output Any-Rate Clock Multipliers with Internal EEPROM General Description Features Input Clocks The MAX24505 and MAX24510 are flexible, high- performance clock multiplier/synthesizer ICs with two One Crystal or CMOS Input independent APLLs. Each APLL performs any-to-any Three Differential or CMOS Inputs frequency conversion. From any input clock frequency Differential to 750MHz, CMOS/TTL to 125MHz 9.72MHz to 750MHz these devices can produce Clock Selection By Pin or Register Control frequency-locked APLL output frequencies up to Two APLLs Plus 5 or 10 Output Clocks 750MHz and as many as 10 differential output clock APLLs Perform High Resolution Fractional-N signals that are integer divisors of the APLL Clock Multiplication frequencies. Output jitter is typically 0.35 to 0.5ps RMS Any Output Frequency from <1Hz to 750MHz (12kHz to 20MHz) on all outputs and can be as low as Each Output Has an Independent Divider 0.24ps RMS. Each device can configure itself from Output Jitter 0.35 to 0.5ps RMS Typical on All internal EEPROM so that clock signals are available Outputs, Can Be As Low As 0.24ps RMS immediately after power-up or reset. Outputs are CML or 2xCMOS, Can Interface to LVDS, LVPECL, HSTL, SSTL and HCSL Applications CMOS Output Voltage from 1.5V to 3.3V Frequency Conversion and Synthesis Applications in a General Features Wide Variety of Equipment Types Automatic Self-Configuration at Power-Up from Internal EEPROM Memory SPI Processor Interface Ordering Information 1.8V + 3.3V Operation (5V Tolerant) PART OUTPUTS PIN-PACKAGE -40 to +85 C Operating Temp. Range 2 MAX24505EXG+ 5 81-CSBGA (10mm) 2 MAX24510EXG+ 10 81-CSBGA (10mm) Block Diagram DIV1 OC1POS/NEG APLL1 A DIV2 OC2POS/NEG 3.7-4.2GHz, Sub-ps jitter, DIV3 OC3POS/NEG B Fractional-N DIV4 OC4POS/NEG DIV5 OC5POS/NEG MAX24510 only IC1POS/NEG APLL2 DIV6 OC6POS/NEG IC2POS/NEG C 3.7-4.2GHz, IC3POS/NEG DIV7 OC7POS/NEG Sub-ps jitter, XIN XO DIV8 OC8POS/NEG Fractional-N XOUT DIV9 OC9POS/NEG MAX24510 only D EEPROM DIV10 OC10POS/NEG SPI Interface JTAG and HW Control and Status Pins 1 RST N TEST INTREQ AC / GPIO1 SS / GPIO2 GPIO3 GPIO4 CS N SCLK SDI SDO JTRST N JTMS JTCLK JTDI JTDOShort Form Data Sheet MAX24505, MAX24510 1. Application Examples Figure 1-1. Asynchronous Ethernet Clocks XIN OC1P/N OC2P/N Any combination of 25MHz, 25MHz OC3P/N 125MHz, 156.25MHz and OC4P/N related Ethernet frequencies XOUT OC5P/N OC6P/N Any combination of differential or OC7P/N 2x single-ended signal format OC8P/N OC9P/N OC10P/N Figure 1-2. Synchronous Ethernet and SDH/SONET Line Card Synchronous Ethernet OC1P/N Clocks: any combination OC2P/N of 25M, 125M, 156.25M OC3P/N 19.44M, OC4P/N and related frequencies 25M, etc. From dual IC1P/N OC5P/N redundant Any combination of differential or IC2P/N timing functions 2x single-ended signal format OC6P/N OC7P/N OC8P/N SDH/SONET Clocks: OC9P/N Nx6.48MHz to 622.08MHz OC10P/N 2