MIC68200-2.5YML TR Microchip

MIC68200 2A Sequencing LDO with Tracking and Ramp Control General Description Features The MIC68200 is a high peak current LDO regulator Stable with 4.7F ceramic capacitor designed specifically for powering applications such Input voltage range: 1.65V to 5.5V as FPGA core voltages that require high start up 0.5V reference current with lower nominal operating current. Capable +1.0% initial output tolerance of sourcing 2A of current for start-up, the MIC68200 provides high power from a small MLF leadless 2A maximum output current peak start up package. The MIC68200 can also implement a variety 1A Continuous Operating Current of power-up and power-down protocols such as Tracking on turn-on and turn-off with pin sequencing, tracking, and ratiometric tracking. strapping The MIC68200 operates from a wide input range of Timing Controlled Sequencing On/Off 1.65V to 5.5V, which includes all of the main supply Programmable Ramp Control for in-rush voltages commonly available today. It is designed to current limiting and slew rate control of the drive digital circuits requiring low voltage at high output voltage on Turn-On and Turn-Off currents (i.e. PLDs, DSP, microcontroller, etc.). The Power-on Reset (POR) supervisor with MIC68200 incorporates a delay pin (DLY) for control programmable delay time of power on reset output (POR) at turn-on and power- Single Master can control multiple Slave down delay at turn-off. In addition there is a ramp regulators with tracking output voltages control pin (RC) for either tracking applications or output voltage slew rate adjustment at turn-on. This is Tiny 3mm x 3mm MLF package important in applications where the load is highly Maximum dropout (V V ) of 400mV over IN OUT capacitive and in-rush currents can cause supply temperature at 1A output current voltages to fail and microprocessors or other complex Fixed and Adjustable Output Voltages logic chips to hang up. Excellent line and load regulation specifications Multiple MIC68200s can be daisy chained in two Logic controlled shutdown modes. In tracking mode the output voltage of the Thermal shutdown and current limit protection Master drives the RC pin of a Slave so that the Slave tracks the main regulator during turn-on and turn-off. In sequencing mode the POR of the Master drives the enable (EN) of the Slave so that it turns on after the Applications Master and turns off before (or after) the Master. This FPGA/PLD Power Supply behavior is critical for power-up and power-down control in multi-output power supplies. The MIC68200 Networking/Telecom Equipment is fully protected offering both thermal and current limit Microprocessor Core Voltage protection and reverse current protection. High Efficiency Linear Post Regulator The MIC68200 has a junction temperature range of Sequenced or Tracked Power Supply 40C to +125C and is available in fixed as well as an adjustable option. The MIC68200 is offered in the tiny 10-pin 3mm x 3mm MLF package. Ramp Control is a trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. MIC68200 Typical Application 2x Processor 47K MIC68200-1.8YML V = 3.3V IN IN OUT I/O U1 4.7F EN EN SNS Master RC DLY GND POR 0.6nF 10nF MIC68200-1.5YML IN OUT U2 CORE 4.7F EN SNS Slave RC /RESET DLY GND POR 1nF 0.7nF U1.EN U1.T DLY U1.TDLY U1.RC U1.TRC U1.DLY U1 Fully Shut Down U1.OUT U2.EN= U1.POR U2.RC U2.TRC U2.DLY U2.T U2.TDLY DLY U2 Fully Shut Down U2.OUT U2.POR Sequenced Dual Power Supply for I/O and Core Voltage of Processor M9999-022311-E 2 February 2011