MIC68220 Dual 2A LDO Regulator General Description Features The MIC68220 is a dual high peak current LDO regulator Stable with 4.7uF ceramic output capacitor designed specifically for powering applications such as Input voltage range: 1.65V to 5.5V FPGA core voltages that require high start up current with 0.5V reference lower nominal operating current. Capable of sourcing 2A of +1.0% initial output tolerance current per channel for start-up, the MIC68220 provides high power from a small MLF leadless package. The 2A maximum output current peak start up MIC68220 can also implement a variety of power-up and 1A Continuous Operating Current power-down protocols such as sequencing, tracking, and Tracking on turn-on and turn-off with pin strapping ratiometric tracking. Timing Controlled Sequencing On/Off The MIC68220 operates from a wide input range of 1.65V Programmable Ramp Control for in-rush current to 5.5V, which includes all of the main supply voltages limiting and slew rate control of the output voltage on commonly available today. It is designed to drive digital Turn-On circuits requiring low voltage at high currents (i.e. PLDs, Power-on Reset (POR) supervisor with programmable DSP, microcontroller, etc.). The MIC68220 incorporates a delay time delay pin (Delay) for control of power on reset output (POR) at turn-on and power-down delay at turn-off. In Single Master can control multiple Slave regulators addition there is a ramp control pin (RC) for either tracking with tracking output voltages applications or output voltage slew rate adjustment at turn- Tiny 4mm x 5mm MLF package on. This is important in applications where the load is Maximum dropout (V V ) of 400mV over IN OUT highly capacitive and in-rush currents can cause supply temperature at 1A output current voltages to fail and microprocessors or other complex logic Adjustable Output Voltages chips to hang up. Excellent line and load regulation specifications The MIC68220s can be configured in two modes. In tracking mode, the output voltage of Vout1 drives the RC2 Logic controlled shutdown pin so that the Vout2 tracks Vout1 during turn-on and turn- Thermal shutdown and current limit protection off. In sequencing mode, POR1 of Vout1 drives the enable pin (EN2) of Vout2 so that it turns on after the Vout1 and Applications turns off before (or after) Vout1. This behavior is critical FPGA/PLD Power Supply for power-up and power-down control in multi-output power supplies. The MIC68220 is fully protected offering Networking/Telecom Equipment both thermal and current limit protection, and reverse Microprocessor Core Voltage current protection. High Efficiency Linear Post Regulator The MIC68220 has a junction temperature range of Sequenced or Tracked Power Supply -40C to +125C and is available in an adjustable Vout1 & Vout2 version. The MIC68220 is offered in a low profile 4mm x 5mm 20ld MLF package. MLF and MicroLeadFrame a registered trademarks of Amkor Technology, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel MIC68220 Typical Application Sequenced Dual Power Supply for I/O and Core Voltage of Processor M9999-092310-C September 2010 2