MT9075BP1 Microchip

MT9075B E1 Single Chip Transceiver Data Sheet August 2011 Features Combined PCM 30 framer, Line Interface Unit Ordering Information (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package MT9075BPR1 68 Pin PLCC* Tape & Reel MT9075BP1 68 Pin PLCC* Tubes Selectable bit rate data link access with optional MT9075BL1 100 Pin MQFP* Trays S bits HDLC controller (HDLC0) and channel 16 a *Pb Free Matte Tin HDLC controller (HDLC1) -40 C to +85 C LIU dynamic range of 20 dB Enhanced performance monitoring and programmable error insertion functions Low jitter DPLL for clock generation Applications Operating under synchronized or free run mode E1 add/drop multiplexers and channel banks Two-frame receive elastic buffer with controlled CO and PBX equipment interfaces slip direction indication Primary Rate ISDN nodes Selectable transmit or receive jitter attenuator Digital Cross-connect Systems (DCS) Intel or Motorola non-multiplexed parallel microprocessor interface CRC-4 updating algorithm for intermediate path points of a message-based data link application ST-BUS/GCI 2.048 Mbit/s backplane bus for both data and signalling TxDL TxDLCLK TxMF TAIS DSTi ST-BUS Transmit Framing, Error and TTIP Line CSTi Interface Test Signal Generation Driver TRING Tdi Tdo PL Loop Tms ST Loop Tclk National Trst Bit Buffer BL/FR INT/MOT Jitter Attenuator BS/LS IRQ & Clock Control OSC1 D7~D0 Data Link, OSC2 CAS AC4 HDLC0, Buffer ~AC0 HDLC1 DG Loop R/W/WR CS RTIP DS/RD RRING DSTo ST-BUS Receive Framing, Performance Monitoring, CSTo Interface Alarm Detection, 2 Frame Slip Buffer RxDLCLK RxDL RxMF LOS RxFP/Rx64kCK E2o F0b C4b Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2011, Zarlink Semiconductor Inc. All Rights Reserved. Microprocessor IEEE 1149.1 Interface Clock,Data Pulse Recovery Generator RM Loop Rx Equalizer & Data Slicer MT LoopMT9075B Data Sheet Description The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for S bits and channel 16. The LIU interfaces the framer functions to the PCM 30 transformer-isolated a four wire line. The MT9075B meets or supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM 30, and I.431 for ISDN primary rate. It also meets or supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233 as well as BS 6450. Change Summary Changes from the August 2005 issue to the August 2011 issue. Page Item Change 1 Ordering Information Removed leaded packages as per PCN notice. 2 Zarlink Semiconductor Inc.