PIC16(L)F18425/45
14/20-Pin Full-Featured, Low Pin Count Microcontrollers
with XLP
Description
PIC16(L)F184XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and
communication peripherals combined with eXtreme Low-Power (XLP) for a wide range of general purpose and low-
2
power applications. Features such as a 12-bit Analog-to-Digital Converter with Computation (ADC ), Memory Access
Partitioning (MAP), the Device Information Area (DIA), Power-Saving operating modes, and Peripheral Pin Select
(PPS), offer flexible solutions for a wide variety of custom applications.
Core Features
C Compiler Optimized RISC Architecture
Operating Speed:
DC 32 MHz clock input
125 ns minimum instruction cycle
Interrupt Capability
16-Level Deep Hardware Stack
Up to Four 8-Bit Timers
Up to Four 16-Bit Timers
Low-Current Power-on Reset (POR)
Configurable Power-up Timer (PWRT)
Brown-out Reset (BOR)
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT):
Variable prescaler selection
Variable window size selection
All sources configurable in hardware or software
Programmable Code Protection
Memory
Up to 28 Kbytes Program Flash Memory
Up to 2 KB Data SRAM Memory
256B Data EEPROM
Direct, Indirect and Relative Addressing Modes
Memory Access Partition (MAP):
Write-protect
Customizable partition
Device Information Area (DIA)
Device Characteristics Information (DCI)
Datasheet DS40002002B-page 1
2019 Microchip Technology Inc. PIC16(L)F18425/45
Operating Characteristics
Operating Voltage Range:
1.8V to 3.6V (PIC16LF184XX)
2.3V to 5.5V (PIC16F184XX)
Temperature Range:
Industrial: -40C to 85C
Extended: -40C to 125C
eXtreme Low-Power (XLP) Features
Doze: CPU and Peripherals Running at Different Cycle Rates (Typically CPU is Lower)
Idle: CPU Halted While Peripherals Operate
Sleep: Lowest Power Consumption
Peripheral Module Disable (PMD):
Ability to selectively disable hardware module to minimize active power consumption of unused peripherals
Extreme Low-Power Mode (XLP)
Sleep: 500 nA typical @ 1.8V
Sleep and Watchdog Timer: 900 nA typical @ 1.8V
Power-Saving Operation Modes
Sleep Mode: 50 nA @ 1.8V, Typical
Watchdog Timer: 500 nA @ 1.8V, Typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
8 uA @ 32 kHz, 1.8V, typical
32 uA/MHz @ 1.8V, typical
Digital Peripherals
Configurable Logic Cell (CLC):
Four CLCs
Integrated combinational and sequential logic
Complementary Waveform Generator (CWG):
Two CWGs
Rising and falling edge dead-band control
Full-bridge, half-bridge, 1-channel drive
Multiple signal sources
Capture/Compare/PWM (CCP) Modules:
Four CCPs
16-bit resolution for Capture/Compare modes
10-bit resolution for PWM mode
Pulse-Width Modulators (PWM):
Two 10-bit PWMs
Numerically Controlled Oscillator (NCO):
Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock
Input Clock: 0 Hz < f < 32 MHz
NCO
20
Resolution: f /2
NCO
DS40002002B-page 2
Datasheet
2019 Microchip Technology Inc.