PIC18F24/25Q10
28-Pin, Low-Power, High-Performance Microcontrollers
Description
PIC18F24/25Q10 microcontrollers feature Analog, Core Independent, and Communication Peripherals for
a wide range of general purpose and low-power applications. These 28 -pin devices are equipped with a
2
10-bit ADC with Computation (ADC ) automating Capacitive Voltage Divider (CVD) techniques for
advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold
comparisons. They also offer a set of Core Independent Peripherals such as Complementary Waveform
Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory
Scan, Zero-Cross Detect (ZCD), and Peripheral Pin Select (PPS), providing for increased design flexibility
and lower system cost.
Core Features
C Compiler Optimized RISC Architecture
Operating Speed:
DC 64 MHz clock input over the full V range
DD
62.5 ns minimum instruction cycle
Programmable 2-Level Interrupt Priority
31-Level Deep Hardware Stack
Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
Four 16-Bit Timers (TMR0/1/3/5)
Low-Current Power-on Reset (POR)
Power-up Timer (PWRT)
Brown-out Reset (BOR)
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT):
Watchdog Reset on too long or too short interval between watchdog clear events
Variable prescaler selection
Variable window size selection
All sources configurable in hardware or software
Memory
Up to 32K Bytes Program Flash Memory
Up to 2048 Bytes Data SRAM Memory
256 Bytes Data EEPROM
Programmable Code Protection
Datasheet Preliminary DS40001945B-page 1
2018 Microchip Technology Inc. PIC18F24/25Q10
Direct, Indirect and Relative Addressing modes
Operating Characteristics
Operating Voltage Range:
1.8V to 5.5V
Temperature Range:
Industrial: -40C to 85C
Extended: -40C to 125C
Power-Saving Operation Modes
Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower)
Idle: CPU Halted While Peripherals Operate
Sleep: Lowest Power Consumption
Peripheral Module Disable (PMD):
Ability to selectively disable hardware module to minimize active power consumption of unused
peripherals
Extreme Low-Power mode (XLP)
Sleep: 500 nA typical @ 1.8V
Sleep and Watchdog Timer: 900 nA typical @ 1.8V
Digital Peripherals
Complementary Waveform Generator (CWG):
Rising and falling edge dead-band control
Full-bridge, half-bridge, 1-channel drive
Multiple signal sources
Capture/Compare/PWM (CCP) modules:
Two CCPs
16-bit resolution for Capture/Compare modes
10-bit resolution for PWM mode
10-Bit Pulse-Width Modulators (PWM):
Two 10-bit PWMs
Serial Communications:
One Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start.
RS-232, RS-485, LIN compatible
SPI
2
I C, SMBus and PMBus compatible
Up to 25 I/O Pins and One Input Pin:
Individually programmable pull-ups
Slew rate control
Interrupt-on-change on all pins
Input level selection control
Programmable CRC with Memory Scan:
DS40001945B-page 2
Datasheet Preliminary
2018 Microchip Technology Inc.