PL500-16SC-R Microchip

PL500-15/16 PL500-15/16 PL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) FEATURES PIN CONFIGURATION XIN 1 8 XOUT VCXO with Divider Selection (DIVSEL) input pin PL500-15: 8, 16 VCON 2 7 OE PL500-16: 2, 4 DIVSEL 3 6 VDD VCXO output for the 1MHz to 18MHz range GND 4 5 CLK 16MHz to 36MHz fundamental crystal input. Low phase noise (-130 dBc 10kHz offset SOP-8L using a 35.328MHz crystal). LVCMOS output with OE tri-state control. Integrated high linearity variable capacitors. VCON 1 6 CLK 12mA drive capability at TTL output. GND 2 5 VDD 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. XIN 3 4 XOUT 2.5V ~ 3.3V operation. SOT23-6L* Available in 8-Pin SOP, 6-pin SOT23 GREEN/ RoHS compliant packages, or DIE. : Denotes internal Pull-up *: SOT package offers single divider option only DESCRIPTION DIVIDER SELECTION LOGIC LEVELS The PL500-15/16 is a low cost, high performance and low phase noise VCXO for the 1MHz to 18MHz Part DivSel State Operation range, providing less than -130dBc at 10kHz offset when using a 35.328MHz crystal. The very low jitter 1 (Default)* 16 PL500-15 (2.5 ps RMS period jitter) makes this chip ideal for 0 8 applications requiring voltage controlled frequency sources. Input crystal can range from 16MHz to 1 (Default)* 4 PL500-16 36MHz (fundamental resonant mode). 0 2 * Setting for SOT23 package BLOCK DIAGRAM DIVSEL XIN Xtal Selectable CLK Osc Divider XOUT VCON Varicap Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 7/01/10 Page 1 PL500-15/16 Low Phase Noise VCXO (1MHz to 18MHz) DIE PAD LAYOUT DIE SPECIFICATIONS 32 mil (812,986) 8 Name Value 1 XIN XOUT OE 7 Size 39 x 32 mil 2 VCON Reverse side GND VDD 6 Pad dimensions 80 micron x 80 micron DIVSEL 3 Thickness 8 mil CLK 5 GND 4 DIE ID: PL500-15: C500A-1111-12 PL500-16: C500A-1111-11 (0,0) Y X Note: denotes internal pull up DIE PAD ASSIGNMENT Pin Die Pad Position Name Type Description SOP-8 SOT23-6 X ( m) Y ( m) XIN 1 3 94.183 768.599 I Crystal input pin. VCON 2 1 94.157 605.029 P Frequency Control Voltage input pin. Divider Selection input pin. Default Logic 1 for DIVSEL 3 - 94.183 331.756 I SOT23 package. See Divider Selection Logic Levels table on Page 1. GND 4 2 94.193 140.379 P Ground pin. CLK 5 6 715.472 203.866 O Output clock pin. VDD 6 5 715.307 455.726 P VDD power supply pin. Output Enable input pin. Disables the output when low. Internal pull-up enables output by OE 7 - 715.472 626.716 I default if pin is not connected to low. Default Enabled (Logic 1) for SOT23 package. XOUT 8 4 476.906 888.881 I Crystal output pin. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 7/01/10 Page 2 39 mil