PL500-37TC-R Microchip

P500-37 PL500-37 (Preliminary)PL500-37 Low Phase Noise VCXO (36MHz to 130MHz) FEATURES PIN AND PAD CONFIGURATION VCXO output for the 36MHz to 130MHz range Low phase noise (-148 dBc @ 10kHz offset at XIN 1 8 XOUT 77.76MHz). OE^ 2 7 DNC CMOS output with OE tri-state control. VCON 3 6 VDD 36 to 130MHz fundamental crystal input. GND CLK Integrated high linearity variable capacitors. 4 5 8mA drive capability at TTL output. SOP-8L +/- 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. Single 2.5V 10% or 3.3V 10 power supply. VCON 1 6 CLK Operating temperature range from -40 C to +85 C GND 2 5 VDD Available in Die or Wafer form or SOP-8L or XIN 3 4 XOUT SOT23-6L packaging. SOT23-6L DESCRIPTION ^: Denotes internal Pull-up The PL500-37 is a low cost, high performance and low phase noise VCXO for the 36 to 130MHz range, providing less than -148dBc at 10kHz offset at 77.76MHz. The very low jitter (2.5 ps RMS period 32 mil (812,986) jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. The input 8 crystal frequency can range from 36 to 130MHz XOUT 1 XIN (fundamental resonant mode). OE^ 7 2 OE^ DIE SPECIFICATIONS VDD 6 Name Value 3 VCON CLK 5 Size 39 x 32 mil 4 GND Reverse side GND Pad dimensions 80 micron x 80 micron (0,0) Y X Thickness 8 mil BLOCK DIAGRAM XIN XTAL OSC XOUT VARICAP OE VCON Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 7/05/10 Page 1 39 mil (Preliminary)PL500-37 Low Phase Noise VCXO (36MHz to 130MHz) PIN AND PAD ASSIGNMENT AND DESCRIPTION Pin# Die Pad Position Name Type Description SOP-8 SOT23-6 X ( m) Y ( m) XIN 1 3 94.183 768.599 I Crystal input pin. Output Enable input pin. Disables the output 2 - 94.157 605.029 when low. Internal pull-up enables output by OE I default if pin is not connected to low. Use only - - 715.472 626.716 one OE signal. VCON 3 1 94.183 331.756 I Frequency control voltage input pin. GND 4 2 94.193 140.379 P Ground pin. CLK 5 6 715.472 203.866 O Output clock pin. VDD power supply pin. Only one VDD pin is VDD 6 5 715.307 455.726 P necessary. DNC 7 - - - I Do Not Connect. No Internal Connection. XOUT 8 4 476.906 888.881 I Crystal output pin. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage V 4.6 V DD Input Voltage, dc V -0.5 V +0.5 V I DD Output Voltage, dc V -0.5 V +0.5 V O DD Storage Temperature T -65 150 C S Ambient Operating Temperature* T -40 85 C A Junction Temperature T 125 C J Lead Temperature (soldering, 10s) 260 C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended per iods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other conditions above the operational limits noted in this specificatio n is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 09/09/05 Page 2