PL602-3x PL602-35/-37/-38/-39 750kHz 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise ICs FEATURES PIN CONFIGURATION (Top View) Selectable 750kHz to 800MHz range. Low phase noise output 1 VDD 1 SEL0 -127dBc/Hz for 155.52MHz 10kHz offset 6 1 XIN 2 SEL1 -115dBc/Hz for 622.08MHz 10kHz offset 5 1 LVCMOS (PL602-37), LVPECL (PL602-35 and XOUT 3 GND 4 PL602-38) or LVDS (PL602-39) output. 1 SEL3 4 CLKC 12MHz to 25MHz crystal input. 3 1 No external crystal load capacitors required. SEL2 5 VDD 2 1 Output Enable selector. OE 6 CLKT 1 Selectable /16 to x32 frequency divider/multiplier. 1 GND 7 GND 0 3.3V operation. GND 8 9 GND Available in 16-Pin TSSOP or 16-pin 3x3mm QFN GREEN/RoHS compliant packages. TSSOP-16L DESCRIPTION The PL602-35 (LVPECL with inverted OE), PL602-37 (LVCMOS), PL602-38 (LVPECL), and PL602-39 (LVDS) are high performance and low phase noise XO IC chips. They provide phase noise performance as low as 127dBc at 10kHz offset (at 155MHz), by multi- 12 11 10 9 XOUT 13 8 GND plying the input crystal frequency up to 32x. The very 14 low jitter makes them ideal for a wide range of applica- 7 CLKC SEL3 PL602-3x tions, including SONET/SDH and FEC. They accept 15 VDD SEL2 6 fundamental parallel resonant mode crystals from 16 5 CLKT OE 12MHz to 25MHz. 1 2 3 4 BLOCK DIAGRAM QFN-16L : Internal pull-up SEL 3:0 *: On QFN package, PL602-35/-38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PL602-37/-39 have SEL0 (pin 10), OE and pin11 is VDD. See pin assignment table for details. Note: On QFN package there is a large center pad for thermal relief. PLL This pad needs to be connected to GND. CLKC Oscillator (Phase Amplifier Locked CLKT OUTPUT ENABLE LOGICAL LEVELS w/ Loop) XIN integrated Part OE State load cap. XOUT 0 (Default) Output enabled PLL by-pass PL602-38 1 Tri-state PL602-3x PL602-35 0 Tri-state PL602-37 1 (Default) Output enabled PL602-39 OE input: Logical states defined by LVPECL levels for PL602-38 Logical states defined by LVCMOS levels for PL602-37/-39 Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 03/07/2012 Page 1 XIN GND GND VDD / GND* GND SEL0 / VDD* GND SEL1 PL602-35/-37/-38/-39 750kHz 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise ICs FREQUENCY SELECTION TABLE SEL3 SEL2 SEL1 SEL0 Selected Multiplier 0 0 1 1 Fin x 32 0 1 1 0 Fin / 8 0 1 1 1 Fin x 2 1 0 0 1 Fin / 2 1 0 1 0 Fin / 16 1 0 1 1 Fin x 4 1 1 0 0 Fin / 4 1 1 0 1 Fin x 8 1 1 1 0 Fin x 16 1 1 1 1 No multiplication Note: SEL0 is not available (always 1) for PL602-35 and PL602-38 in 3x3mm package PIN DESCRIPTIONS PL602-35 and PL602-38 (see next page for PL602-37/-39) TSSOP 3x3mm QFN Name Type Description Pin number Pin number XIN 2 12 I Crystal input (See Crystal Specification on page 4) XOUT 3 13 I Crystal output (See Crystal Specification on page 4) OE 6 16 I Output enable pin (See OE logic state table on page 1) GND 7,8,9,10,14 1,2,3,4,8,11 P Ground connection CLKT 11 5 O LVPECL True output CLKC 13 7 O LVPECL Complementary output SEL0 16 Not available I Multiplier selector pins. These pins have an internal pull- SEL1 15 9 I up that will default SEL to 1 when not connected to SEL2 5 15 I GND. SEL3 4 14 I VDD 1, 12 6,10 P +3.3V power supply. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 03/07/2012 Page 2