PL611-01 PL611-01 Programming Logic PL611-01 TM Programmable Clock FEATURES PIN CONFIGURATION Advanced programmable PLL design Very low Jitter and Phase Noise (30-70ps Pk-Pk typical) XIN,F IN 1 8 XOUT Up to 3 programmable outputs GND 2 7 CLK2, OE ,P DB , FSEL Output frequency up to 200MHz CMOS. CLK0 3 6 NC Accepts Crystal or reference clock inputs o Fundamental crystal: 10MHz-30MHz CLK1 4 5 VDD RD o 3 overtone crystal: Up to 75MHz o Reference input: Up to 200MHz SOP-8 MSOP-8 Accepts <1.0V reference signal input voltage One programmable I/O pin can be configured as Programmable clock, or Frequency Selection input, CLK1 VDD 1 6 or output Enable (OE) or Power Down (PDB) input. GND Supply operating range 2.25V to 3.63V 2 5 CLK2, OE , P DB , FSEL Operating temperature range from -40 C to 85 C XIN, FIN XOUT 3 4 Available in 8-pin MSOP/SOP, and 6-pin SOT Green/ RoHS compliant Packages SOT-6 DESCRIPTION The PL611-01 is a low-cost general purpose frequency synthesizer and a member of Programmable Clock family. PL611-01 product family offers the versatility of using a single Crystal or Reference Clock input and producing up to three different system clocks. They can generate any output frequency up to 200 MHz from fundamental crystal input between 10 MHz - 30 MHz, or a 3rd overtone crystal of up to 75Mhz, or a Reference clock input of up to 200 MHz. Cascading of the ICs to produce additional clock frequencies is also supported . BLOCK DIAGRAM XIN, FIN F Ref Xtal R - counter . OSC ( 8 - bit ) XOUT Phase Charge Loop Detector Pump Filter M - counter ( 10- bit ) F = F * (2 * M /R) VCO Ref. VCO P - counter ( 5 - bit ) FSEL Selectable OE / 1 , / 2 , /4 , / 8 F = F / (2 * P) out VCO PDB CLOCK 0:2 CLoad Selectable /1 , / 2 Programmable Function Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev.01/20/12 Page 1 PL611-01 TM Programmable Clock KEY PROGRAMMING PARAMETERS CLK 0:2 Output Drive Crystal Programmable Charge-Pump Output Frequency Strength Load Input/Output Current F = F * M / (R * P) Std: 10mA (default) +/- 200ppm One output pin can 4 levels of OUT REF where M=10 bit tuning. be configured as pump current R= 8 bit High: 24mA 1. CLK2 - output settings P= 5 bit 2. FSEL - input CLK 0:2 = Fout / (1,2,4,8), F or 3. OE - input REF F / 2 4. PDB - input REF PIN DESCRIPTION Pin Name Type Description MSOP-8 SOT-23 SOIC-8 XIN, FIN 1 3 I Crystal or Reference input pin GND 2 2 P GND connection CLK 0:1 3,4 1 O Programmable Clock Output VDD 5 6 P VDD connection (2.25~3.63V) NC 6 No Connect This programmable I/O pin can be configured as a programmable clock output (CLK2), or Output Enable (OE) input, or Power Down input (PDB), or Frequency Selection (FSEL) input pin. This pin has an internal 60K pull up resistor. CLK2, OE, PDB, FSEL 7 5 B State OE PDB FSEL Tristate Power Select Freq. 0 CLK 0:1 Down Mode 1 1 Normal Normal Select Freq. (default) mode mode 2 XOUT 8 4 O Crystal output pin Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev.01/20/12 Page 2