64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 SST38VF640x2.7V 64Mb (x16) MPF+ memories Preliminary Specification FEATURES: Organized as 4M x16 Latched Address and Data Single Voltage Read and Write Operations Fast Erase Times: 2.7-3.6V Sector-Erase Time: 18 ms (typical) Block-Erase Time: 18 ms (typical) Superior Reliability Chip-Erase Time: 40 ms (typical) Endurance: up to 100,000 Cycles minimum Erase-Suspend/-Resume Capabilities Greater than 100 years Data Retention Fast Word and Write-Buffer Programming Low Power Consumption (typical values at 5 MHz) Times: Active Current: 4 mA (typical) Word-Program Time: 7 s (typical) Standby Current: 3 A (typical) Write Buffer Programming Time: 1.75 s / Word Auto Low Power Mode: 3 A (typical) (typical) 128-bit Unique ID - 16-Word Write Buffer Security-ID Feature Automatic Write Timing 256 Word, user One-Time-Programmable Internal V Generation PP Protection and Security Features End-of-Write Detection Hardware Boot Block Protection/WP Input Pin, Toggle Bits Uniform (32 KWord) and Non-Uniform (8 KWord) Data Polling options available RY/BY Output User-controlled individual block (32 KWord) pro- CMOS I/O Compatibility tection, using software only methods Password protection JEDEC Standard Hardware Reset Pin (RST ) Flash EEPROM Pinouts and command sets Fast Read and Page Read Access Times: CFI Compliant 90 ns Read access time Packages Available 25 ns Page Read access times 48-lead TSOP - 4-Word Page Read buffer 48-ball TFBGA All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST38VF6401, SST38VF6402, SST38VF6403, and To protect against inadvertent write, the SST38VF6401/ SST38VF6404 devices are 4M x16 CMOS Advanced 6402/6403/6404 have on-chip hardware and Software Multi-Purpose Flash Plus (Advanced MPF+) manufactured Data Protection schemes. Designed, manufactured, and with SST proprietary, high-performance CMOS Super- tested for a wide spectrum of applications, these devices Flash technology. The split-gate cell design and thick-oxide are available with up to 100,000 cycles minimum endur- tunneling injector attain better reliability and manufacturabil- ance. Data retention is rated at greater than 100 years. ity compared with alternate approaches. The The SST38VF6401/6402/6403/6404 are suited for applica- SST38VF6401/6402/6403/6404 write (Program or Erase) tions that require the convenient and economical updating with a 2.7-3.6V power supply. These devices conform to of program, configuration, or data memory. For all system JEDEC standard pin assignments for x16 memories. applications, Advanced MPF+ significantly improve perfor- Featuring high performance Word-Program, the mance and reliability, while lowering power consumption. SST38VF6401/6402/6403/6404 provide a typical Word- These devices inherently use less energy during Erase and Program time of 7 sec. For faster word-programming per- Program than alternative flash technologies. The total formance, the Write-Buffer Programming feature, has a typ- energy consumed is a function of the applied voltage, cur- ical word-program time of 1.75 sec. These devices use rent, and time of application. For any given voltage range, Toggle Bit or Data Polling to indicate Program operation the SuperFlash technology uses less current to program completion. In addition to single-word Read, Advanced and has a shorter erase time therefore, the total energy MPF+ devices provide a Page-Read feature that enables a consumed during any Erase or Program operation is less faster word read time of 25 ns, for words on the same page. than alternative flash technologies. 2009 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71309-04-000 1/09 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice.64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404 Preliminary Specification These devices also improve flexibility while lowering the when either CE or OE is high. Refer to Figure 5, the cost for program, data, and configuration storage applica- Read cycle timing diagram, for further details. tions. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Pro- Page Read gram cycles that have occurred. Therefore, the system soft- The Page Read operation utilizes an asynchronous ware or hardware does not have to be modified or de-rated method that enables the system to read data from the as is necessary with alternative flash technologies, whose SST38VF6401/6402/6403/6404 at a faster rate. This oper- Erase and Program times increase with accumulated ation allows users to read a four-word page of data at an Erase/Program cycles. average speed of 41.25 ns per word. The SST38VF6401/6402/6403/6404 also offer flexible data In Page Read, the initial word read from the page requires protection features. Applications that require memory pro- T to be valid, while the remaining three words in the ACC tection from program and erase operations can use the page require only T . All four words in the page have PACC Boot Block, Individual Block Protection, and Advanced Pro- the same address bits, A -A , which are used to select the 21 2 tection features. For applications that require a permanent page. Address bits A and A are toggled, in any order, to 1 0 solution, the Irreversible Block Locking feature provides read the words within the page. permanent protection for memory blocks. The Page Read operation of the SST38VF6401/6402/ To meet high-density, surface mount requirements, the 6403/6404 is controlled by CE and OE . Both CE and SST38VF6401/6402/6403/6404 devices are offered in 48- OE must be low for the system to obtain data from the lead TSOP and 48-ball TFBGA packages. See Figures 2 output pins. CE controls device selection. When CE is and 3 for pin assignments and Table 7 for pin descriptions. high, the chip is deselected and only standby power is con- sumed. OE is the output control and is used to gate data DEVICE OPERATION from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to Figure 6, The memory operations functions of these devices are initi- the Page Read cycle timing diagram, for further details. ated using commands written to the device using standard microprocessor Write sequences. A command is written by Word-Program Operation asserting WE low while keeping CE low. The address bus is latched on the falling edge of WE or CE , which- The SST38VF6401/6402/6403/6404 can be programmed ever occurs last. The data bus is latched on the rising edge on a word-by-word basis. Before programming, the sector of WE or CE , whichever occurs first. where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the The SST38VF6401/6402/6403/6404 also have the Auto three-byte load sequence for Software Data Protection. The Low Power mode which puts the device in a near-standby second step is to load word address and word data. During mode after data has been accessed with a valid Read the Word-Program operation, the addresses are latched on operation. This reduces the I active read current from DD the falling edge of either CE or WE , whichever occurs last. typically 4 mA to typically 3 A. The Auto Low Power mode The data is latched on the rising edge of either CE or WE , reduces the typical I active read current to the range of 2 DD whichever occurs first. The third step is the internal Program mA/MHz of Read cycle time. The device requires no operation which is initiated after the rising edge of the fourth access time to exit the Auto Low Power mode after any WE or CE , whichever occurs first. The Program operation, address transition or control signal transition used to initiate once initiated, will be completed within 10 s. See Figures 7 another Read cycle. The device does not enter Auto-Low and 8 for WE and CE controlled Program operation timing Power mode after power-up with CE held steadily low, diagrams and Figure 24 for flowcharts. until the first address transition or CE is driven high. During the Program operation, the only valid reads are Data Polling, Toggle Bits, and RY/BY . During the internal Read Program operation, the host is free to perform additional The Read operation of the SST38VF6401/6402/6403/ tasks. Any commands issued during the internal Program 6404 is controlled by CE and OE , both of which have operation are ignored. During the command sequence, to be low for the system to obtain data from the outputs. WP should be statically held high or low. CE is used for device selection. When CE is high, the chip is deselected and only standby power is consumed. When programming more than a few words, SST recom- OE is the output control and is used to gate data from mends Write-Buffer Programming. the output pins. The data bus is in high impedance state 2009 Silicon Storage Technology, Inc. S71309-04-000 1/09 2