2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A SST39LF/VF200A / 400A / 800A3.0 & 2.7V 2Mb / 4Mb / 8Mb (x16) MPF memories Data Sheet FEATURES: Organized as 128K x16 / 256K x16 / 512K x16 Fast Erase and Word-Program Single Voltage Read and Write Operations Sector-Erase Time: 18 ms (typical) Block-Erase Time: 18 ms (typical) 3.0-3.6V for SST39LF200A/400A/800A Chip-Erase Time: 70 ms (typical) 2.7-3.6V for SST39VF200A/400A/800A Word-Program Time: 14 s (typical) Superior Reliability Chip Rewrite Time: Endurance: 100,000 Cycles (typical) 2 seconds (typical) for SST39LF/VF200A Greater than 100 years Data Retention 4 seconds (typical) for SST39LF/VF400A 8 seconds (typical) for SST39LF/VF800A Low Power Consumption (typical values at 14 MHz) Automatic Write Timing Active Current: 9 mA (typical) Internal V Generation PP Standby Current: 3 A (typical) End-of-Write Detection Sector-Erase Capability Toggle Bit Uniform 2 KWord sectors Data Polling Block-Erase Capability CMOS I/O Compatibility Uniform 32 KWord blocks JEDEC Standard Fast Read Access Time Flash EEPROM Pinouts and command sets 55 ns for SST39LF200A/400A/800A Packages Available 70 ns for SST39VF200A/400A/800A 48-lead TSOP (12mm x 20mm) Latched Address and Data 48-ball TFBGA (6mm x 8mm) 48-ball WFBGA (4mm x 6mm) 48-bump XFLGA (4mm x 6mm) 4 and 8Mbit All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST39LF200A/400A/800A and SST39VF200A/400A/ The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A devices are 128K x16 / 256K x16 / 512K x16 CMOS 800A devices are suited for applications that require con- Multi-Purpose Flash (MPF) manufactured with SST propri- venient and economical updating of program, configura- etary, high-performance CMOS SuperFlash technology. tion, or data memory. For all system applications, they The split-gate cell design and thick oxide tunneling injector significantly improve performance and reliability, while low- attain better reliability and manufacturability compared with ering power consumption. They inherently use less energy alternate approaches. The SST39LF200A/400A/800A during Erase and Program than alternative flash technolo- write (Program or Erase) with a 3.0-3.6V power supply. gies. When programming a flash device, the total energy The SST39VF200A/400A/800A write (Program or Erase) consumed is a function of the applied voltage, current, and with a 2.7-3.6V power supply. These devices conform to time of application. Since for any given voltage range, the JEDEC standard pinouts for x16 memories. SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed dur- Featuring high-performance Word-Program, the ing any Erase or Program operation is less than alternative SST39LF200A/400A/800A and SST39VF200A/400A/ flash technologies. These devices also improve flexibility 800A devices provide a typical Word-Program time of 14 while lowering the cost for program, data, and configura- sec. The devices use Toggle Bit or Data Polling to detect tion storage applications. the completion of the Program or Erase operation. To pro- tect against inadvertent write, they have on-chip hardware The SuperFlash technology provides fixed Erase and Pro- and software data protection schemes. Designed, manu- gram times, independent of the number of Erase/Program factured, and tested for a wide spectrum of applications, cycles that have occurred. Therefore the system software these devices are offered with a guaranteed typical endur- or hardware does not have to be modified or de-rated as is ance of 100,000 cycles. Data retention is rated at greater necessary with alternative flash technologies, whose than 100 years. Erase and Program times increase with accumulated Erase/Program cycles. 2010 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71117-12-000 04/10 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice.2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A Data Sheet To meet surface mount requirements, the SST39LF200A/ Sector/Block-Erase Operation 400A/800A and SST39VF200A/400A/800A are offered in The Sector- (or Block-) Erase operation allows the system 48-lead TSOP packages and 48-ball TFBGA packages as to erase the device on a sector-by-sector (or block-by- well as Micro-Packages. See Figures 2, 3, and 4 for pin block) basis. The SST39LF200A/400A/800A and assignments. SST39VF200A/400A/800A offers both Sector-Erase and Block-Erase mode. The sector architecture is based on Device Operation uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector- Commands are used to initiate the memory operation func- Erase operation is initiated by executing a six-byte com- tions of the device. Commands are written to the device mand sequence with Sector-Erase command (30H) and using standard microprocessor write sequences. A com- sector address (SA) in the last bus cycle. The Block-Erase mand is written by asserting WE low while keeping CE operation is initiated by executing a six-byte command low. The address bus is latched on the falling edge of WE sequence with Block-Erase command (50H) and block or CE , whichever occurs last. The data bus is latched on address (BA) in the last bus cycle. The sector or block the rising edge of WE or CE , whichever occurs first. address is latched on the falling edge of the sixth WE pulse, while the command (30H or 50H) is latched on the Read rising edge of the sixth WE pulse. The internal Erase The Read operation of the SST39LF200A/400A/800A and operation begins after the sixth WE pulse. The End-of- SST39VF200A/400A/800A is controlled by CE and OE , Erase operation can be determined using either Data both have to be low for the system to obtain data from the Polling or Toggle Bit methods. See Figures 11 and 12 for outputs. CE is used for device selection. When CE is timing waveforms. Any commands issued during the Sec- high, the chip is deselected and only standby power is con- tor- or Block-Erase operation are ignored. sumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance Chip-Erase Operation state when either CE or OE is high. Refer to the Read The SST39LF200A/400A/800A and SST39VF200A/400A/ cycle timing diagram for further details (Figure 5). 800A provide a Chip-Erase operation, which allows the user to erase the entire memory array to the 1 state. This Word-Program Operation is useful when the entire device must be quickly erased. The SST39LF200A/400A/800A and SST39VF200A/400A/ The Chip-Erase operation is initiated by executing a six- 800A are programmed on a word-by-word basis. Before byte command sequence with Chip-Erase command (10H) programming, the sector where the word exists must be at address 5555H in the last byte sequence. The Erase fully erased. The Program operation is accomplished in operation begins with the rising edge of the sixth WE or three steps. The first step is the three-byte load sequence CE , whichever occurs first. During the Erase operation, for Software Data Protection. The second step is to load the only valid read is Toggle Bit or Data Polling. See Table word address and word data. During the Word-Program 4 for the command sequence, Figure 10 for timing diagram, operation, the addresses are latched on the falling edge of and Figure 21 for the flowchart. Any commands issued dur- either CE or WE , whichever occurs last. The data is ing the Chip-Erase operation are ignored. latched on the rising edge of either CE or WE , whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE or Write Operation Status Detection CE , whichever occurs first. The Program operation, once The SST39LF200A/400A/800A and SST39VF200A/400A/ initiated, will be completed within 20 s. See Figures 6 and 800A provide two software means to detect the completion 7 for WE and CE controlled Program operation timing of a write (Program or Erase) cycle, in order to optimize the diagrams and Figure 18 for flowcharts. During the Program system write cycle time. The software detection includes operation, the only valid reads are Data Polling and Tog- two status bits: Data Polling (DQ ) and Toggle Bit (DQ ). 7 6 gle Bit. During the internal Program operation, the host is The End-of-Write detection mode is enabled after the rising free to perform additional tasks. Any commands issued edge of WE , which initiates the internal Program or Erase during the internal Program operation are ignored. operation. 2010 Silicon Storage Technology, Inc. S71117-12-000 04/10 2