SST49LF160C-33-4C-NHE Microchip

Obsolete Device Please contact Microchip Sales for replacement information. 16 Mbit LPC Flash SST49LF160C EOL Data Sheet SST49LF160C flash memory device is designed to interface with host controllers (chipsets) that support a low pin-count (LPC) interface for system firmware appli- cations. SST49LF160C device complies with the LPC Interface Specification. The LPC interface operates with 5 signal pins versus 32 pins of a 8-bit parallel flash memory. This frees up pins on the ASIC host controller resulting in lower ASIC costs and a reduction in overall system costs due to simplified signal routing. Features Organized as 2M x8 Superior Reliability Endurance: 100,000 Cycles (typical) Conforms to LPC Interface Specification Greater than 100 years Data Retention Support Single-Byte LPC Memory Read/Write Cycles Low Power Consumption Single 3.0-3.6V Read and Write Operations Active Read Current: 12 mA (typical) Standby Current: 10 A (typical) LPC Mode Uniform 4 KByte sectors 5-signal LPC bus interface for both in-system and fac- tory programming using programmer equipment 35 Overlay Blocks: one 16-KByte Boot Block, two 8- 33 MHz clock frequency operation KByte Parameter Blocks, one 32-Kbyte Parameter WP /AAI and TBL pins provide hardware Write protect Block, thirty-one 64-KByte Main Blocks. for entire chip and/or top Boot Block Block Locking Registers for individual block Read-Lock, Fast Sector-Erase/Program Operation Write-Lock, and Lock-Down protection Sector-Erase Time: 18 ms (typical) 5 GPI pins for system design flexibility Block-Erase Time: 18 ms (typical) 4 ID pins for multi-chip selection Program Time: 7 s (typical) Status register for End-of-Write detection Program-/Erase-Suspend Auto Address Increment (AAI) for Rapid Factory Read or Write to other blocks during Programming (High Voltage Enabled) Program-/Erase-Suspend RY/BY pin for End-of-Write detection Multi-Byte Program Two-cycle Command Set Chip Rewrite Time: 4 seconds (typical) Security ID Feature Packages Available 256-bit Secure ID space 32-lead PLCC - 64-bit Unique Factory Pre-programmed Device Identi- fier All non-Pb (lead-free) devices are RoHS compliant - 192-bit User-Programmable OTP 2016 www.microchip.com DS20005099B 02/1616 Mbit LPC Flash SST49LF160C EOL Data Sheet Product Description The SST49LF160C flash memory device is designed to interface with host controllers (chipsets) that support a low-pin-count (LPC) interface for system firmware applications. The SST49LF160C device complies with the LPC Interface Specification. The LPC interface operates with 5 signal pins versus 32 pins of a 8-bit parallel flash memory. This frees up pins on the ASIC host controller resulting in lower ASIC costs and a reduction in overall system costs due to simplified signal routing. The SST49LF160C uses a 5-signal LPC interface to support both in-system and rapid factory program- ming using programmer equipment. A high voltage pin (WP /AAI) is used to enable Auto Address Increment (AAI) mode. The SST49LF160C offers hardware block protection in addition to individual block protection via software registers for critical system code and data. A 256-bit Security ID space with a 64-bit factory pre-programmed unique number and a 192-bit user programmable OTP area enhances the users ability to use new security techniques and implement a new data protection scheme. The SST49LF160C also provides general purpose inputs (GPI) for system design flexibility. The SST49LF160C flash memory device is manufactured with SSTs proprietary, high-performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain greater reliability and manufacturability compared with alternative technology approaches. The SST49LF160C device significantly improves performance and reliability, while lowering power consumption. The SST49LF160C device writes (Program or Erase) in-system with a single 3.0-3.6V power supply. It uses less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SuperFlash technology provides fixed Erase and Program time, independent of the number of Erase/Program cycles that have performed. Therefore the system software or hardware does not have to be calibrated or correlated to the cumulative number of erase cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/Pro- gram cycles. To protect against inadvertent write, the SST49LF160C device has on-chip hardware and software write protection schemes. It is offered with a typical endurance of 100,000 cycles. Data reten- tion is rated at greater than 100 years. The SST49LF160C product provides a maximum program time of 10 s per byte with a single-byte Program operation effectively 5 s per byte with a dual-byte Program operation and 2.5 s per byte with a quad-byte Program operation. End-of-Write can be detected by the RY/BY pin output in AAI mode and by reading the software status register during an in-system Program or Erase operation. The SST49LF160C is offered in a 32-PLCC lead-free package to address the growing need for non-Pb solutions in electronic components. Non-Pb package versions can be obtained by ordering products with a package code suffix of E as the environmental attribute in the product part number. See Figure 3 for pin assignments and Table 1 for pin descriptions. 2016 DS20005099B 02/16 2