SST89E516RD2-40-I-NJE Microchip

Notrecommendedfornewdesigns.ContactMicrochip Sales for microcontroller design options. FlashFlex MCU SST89E516RD2 / SST89E516RD A Microchip Technology Company SST89V516RD2 / SST89V516RD Data Sheet The SST89E516RDx and SST89V516RDx are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SSTs patented and proprietary SuperFlash CMOS semiconductor process technology. The split- gate cell design and thick-oxide tunneling injector offer significant cost and reli- ability benefits for SSTs customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices. Features 8-bit 8051-Compatible Microcontroller (MCU) with Programmable Watchdog Timer (WDT) Embedded SuperFlash Memory Programmable Counter Array (PCA) Fully Software Compatible Development Toolset Compatible Four 8-bit I/O Ports (32 I/O Pins) and Pin-For-Pin Package Compatible One 4-bit Port SST89E516RD2 Operation Second DPTR register 0 to 40 MHz at 5V LowEMIMode(InhibitALE) SST89V516RD2 Operation 0 to 33 MHz at 3V SPI Serial Interface 1 KByte Internal RAM Standard 12 Clocks per cycle, the device has an option to double the speed to 6 clocks per cycle. Dual Block SuperFlash EEPROM 64 KByte primary block + TTL- and CMOS-Compatible Logic Levels 8 KByte secondary block (128-Byte sector size for both blocks) Brown-out Detection Individual Block Security Lock with SoftLock Concurrent Operation during Low Power Modes In-Application Programming (IAP) Memory Overlay for Interrupt Support during IAP Power-downModewithExternalInterruptWake-up Idle Mode Support External Address Range up to 64 KByte Temperature Ranges: of Program and Data Memory Commercial (0C to +70C) Three High-Current Drive Ports (16 mA each) Industrial (-40C to +85C) Three 16-bit Timers/Counters Packages Available 40-contact WQFN (Port 4 feature not available) Full-Duplex, Enhanced UART 44-lead PLCC 40-pin PDIP (Port 4 feature not available) Framing Error Detection 44-lead TQFP Automatic Address Recognition Allnon-Pb(lead-free)devicesareRoHScompliant Ten Interrupt Sources at 4 Priority Levels Four External Interrupt Inputs 2011 Silicon Storage Technology, Inc. www.microchip.com DS25093A 11/11FlashFlex MCU SST89E516RD2 / SST89E516RD SST89V516RD2 / SST89V516RD A Microchip Technology Company Data Sheet Product Description The SST89E516RDx and SST89V516RDx are members of the FlashFlex family of 8-bit microcon- troller products designed and manufactured with SSTs patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SSTs customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices. The devices come with 72 KByte of on-chip flash EEPROM program memory which is partitioned into 2 independent program memory blocks. The primary Block 0 occupies 64 KByte of internal program memory space and the secondary Block 1 occupies 8 KByte of internal program memory space. The 8-KByte secondary block can be mapped to the lowest location of the 64 KByte address space it can also be hidden from the program counter and used as an independent EEPROM-like data mem- ory. In addition to the 72 KByte of EEPROM program memory on-chip and 1024 x8 bits of on-chip RAM, the devices can address up to 64 KByte of external program memory and up to 64 KByte of external RAM. The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and the firmware for SSTs devices. During power-on reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-application programming (IAP) operation. The devices are designed to be programmed in- system and in-application on the printed circuit board for maximum flexibility. The devices are pre-pro- grammed with an example of the bootstrap loader in the memory, demonstrating the initial user pro- gram code loading or subsequent user code updating via the IAP operation. The sample bootstrap loader is available for the users reference and convenience only SST does not guarantee its function- ality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code. 2011 Silicon Storage Technology, Inc. DS25093A 11/11 2