SST89E54RD2A-40-C-NJE Microchip

Notrecommendedfornewdesigns.ContactMicrochip Sales for microcontroller design options. FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Not Recommended for New Designs The SST89E54RD2A/RDA and SST89E58RD2A/RDA are members of the Flash- Flex family of 8-bit microcontroller products designed and manufactured with SST patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices. Features 8-bit 8051-Compatible Microcontroller (MCU) with Programmable Counter Array (PCA) Embedded SuperFlash Memory Four 8-bit I/O Ports (32 I/O Pins) and Fully Software Compatible One 4-bit Port Development Toolset Compatible Pin-For-Pin Package Compatible Second DPTR register SST89E5xRD2A Operation LowEMIMode(InhibitALE) 0 to 40 MHz at 5V SPI Serial Interface 1 KByte Internal RAM Standard 12 Clocks per cycle, the device has an Dual Block SuperFlash EEPROM option to double the speed to 6 clocks per cycle. 16/32 KByte primary block + 8 KByte secondary block TTL- and CMOS-Compatible Logic Levels (128-Byte sector size for both blocks) Individual Block Security Lock with SoftLock Brown-out Detection Concurrent Operation during In-Application Programming (IAP) Memory Overlay for Interrupt Support during IAP Low Power Modes Power-downModewithExternalInterruptWake-up Support External Address Range up to 64 KByte Idle Mode of Program and Data Memory Temperature Ranges: Three High-Current Drive Ports (16 mA each) Commercial (0C to +70C) Three 16-bit Timers/Counters Packages Available 44-lead PLCC Full-Duplex, Enhanced UART 40-pin PDIP (Port 4 feature not available) Framing Error Detection 44-lead TQFP Automatic Address Recognition Allnon-Pb(lead-free)devicesareRoHScompliant Ten Interrupt Sources at 4 Priority Levels Four External Interrupt Inputs Programmable Watchdog Timer (WDT) 2011 Silicon Storage Technology, Inc. www.microchip.com DS25114A 12/11FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA A Microchip Technology Company Not Recommended for New Designs Product Description The SST89E54RD2A/RDA and SST89E58RD2A/RDA are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SST patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SST customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices. The devices come with 24/40 KByte of on-chip flash EEPROM program memory which is partitioned into 2 independent program memory blocks. The primary Block 0 occupies 16/32 KByte of internal pro- gram memory space and the secondary Block 1 occupies 8 KByte of internal program memory space. The 8-KByte secondary block can be mapped to the lowest location of the 16/32 KByte address space it can also be hidden from the program counter and used as an independent EEPROM-like data mem- ory. In addition to the 24/40 KByte of EEPROM program memory on-chip and 1024 x8 bits of on-chip RAM, the devices can address up to 64 KByte of external program memory and up to 64 KByte of external RAM. The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and the firmware for SST devices. During power-on reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-application programming (IAP) operation. The devices are designed to be programmed in- system and in-application on the printed circuit board for maximum flexibility. The devices are pre-pro- grammed with an example of the bootstrap loader in the memory, demonstrating the initial user pro- gram code loading or subsequent user code updating via the IAP operation. The sample bootstrap loader is available for the users reference and convenience only SST does not guarantee its function- ality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code. 2011 Silicon Storage Technology, Inc. DS25114A 12/11 2