NOT RECOMMENDED FOR NEW DESIGNS Precision Edge Micrel, Inc. SY100S811 SINGLE SUPPLY 1:9 Precision Edge SY100S811 PECL/TTL-TO-PECL FEATURES PECL version of popular ECLinPS E111 Precision Edge Low skew Guaranteed skew spec DESCRIPTION VBB output TTL enable input The SY100S811 is a low skew 1-to-9 PECL differential driver designed for clock distribution in new, high- Selectable TTL or PECL clock input performance PECL systems. It accepts either a PECL Single +5V supply clock input or a TTL input by using the TTL enable pin TEN. Differential internal design When the TTL enable pin is HIGH, the TTL input is enabled Similar pin configuration to E111 and the PECL input is disabled. When the enable pin is set LOW, the TTL input is disabled and the PECL input is PECL I/O fully compatible with industry standard enabled. Internal 75K PECL input pull-down resistors The device is specifically designed and produced for low Available in 28-pin PLCC and SOIC packages skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot BLOCK DIAGRAM to lot. Since the S811 shares a common set of basic processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization Q0 allows for tighter control of parameters, including Q0 propagation delay. To ensure that the skew specification is met, it is Q1 necessary that both sides of the differential output are EIN Q1 terminated into 50 , even if only one side is being used. ln 0 EIN Q2 most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than Q2 nine pairs are used, it is necessary to terminate at least the Q3 output pairs on the same package side (i.e. sharing the TIN 1 Q3 same VCCO as the pair(s) being used on that side) in order to maintain minimum skew. Q4 The VBB output is intended for use as a reference Q4 voltage for single-ended reception of PECL signals to that TEN Q5 device only. When using VBB for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01 F Q5 capacitor. Q6 Q6 Q7 Q7 Q8 Q8 VBB Precision Edge is a registered trademark of Micrel, Inc. Rev.: H Amendment: /0 M9999-021407 1 Issue Date: February 2007 hbwhelp micrel.com or (408) 955-1690 Precision Edge Micrel, Inc. SY100S811 PACKAGE/ORDERING INFORMATION Ordering Information Package Operating Package Lead 25 24 23 22 21 20 19 Part Number Type Range Marking Finish VEE 26 18 Q3 SY100S811ZC Z28-1 Commercial SY100S811ZC Sn-Pb 27 17 TEN Q3 (1) SY100S811ZCTR Z28-1 Commercial SY100S811ZC Sn-Pb 28 16 EIN Q4 TOP VIEW VCC 1 PLCC 15 VCCO SY100S811JC J28-1 Commercial SY100S811JC Sn-Pb J28-1 2 14 EIN Q4 (1) SY100S811JCTR J28-1 Commercial SY100S811JC Sn-Pb VBB 3 13 Q5 (2) 4 12 TIN Q5 SY100S811ZH Z28-1 Commercial SY100S811ZH with NiPdAu 56 7 8 9 1011 Pb-Free bar-line indicator Pb-Free (1, 2) SY100S811ZHTR Z28-1 Commercial SY100S811ZH with NiPdAu Pb-Free bar-line indicator Pb-Free (2) SY100S811JZ J28-1 Commercial SY100S811JZ with Matte-Sn 28-Pin PLCC (J28-1) Pb-Free bar-line indicator (1, 2) SY100S811JZTR J28-1 Commercial SY100S811JZ with Matte-Sn Pb-Free bar-line indicator 28 VCC 1 Notes: EIN 1. Tape and Reel. 27 2 EIN TEN 2. Pb-Free package is recommended for new designs. 3 26 VBB VEE TIN 4 25 Q0 5 24 Q8 Q0 23 6 Q8 Q1 TOP VIEW 7 22 VCCO Q7 SOIC Z28-1 21 8 VCCO Q1 9 20 Q7 Q2 19 10 Q6 Q2 11 18 Q6 Q3 17 12 Q5 Q3 Q5 13 16 Q4 14 15 VCCO Q4 28-Pin SOIC (Z28-1) M9999-021407 2 hbwhelp micrel.com or (408) 955-1690 Q8 Q0 Q8 Q0 Q1 Q7 VCCO VCCO Q7 Q1 Q6 Q2 Q6 Q2