SY100S834LZG Microchip

SY100S834L 3.3V 2, 4, 8 Clock Generation Chip Features General Description 3.3V Power Supply The SY100S834L is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock 5 0 ps Output to Output Skew generation applications. The internal dividers are Synchronous Enable/Disable synchronous to each other therefore, the common Master Reset for Synchronization output edges are all precisely aligned. The devices can Internal 75 k Input Pull Down Resistors be driven by either a differential or single-ended ECL Available in 16-Pin SOIC Package or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If Package Type a single-ended input is to be used, the VBB output should be connected to the input and bypassed to SY100S834L ground via a 0.01 F capacitor. The VBB output is 16-Lead Narrow SOIC (Z16-2) designed to act as the switching reference for the input of the SY100S834L under single-ended input conditions. As a result, this pin can only source/sink up VCC Q0 to 0.5 mA of current. The Function Select (FSEL) input is used to determine /EN /Q0 what clock generation chip function is. When FSEL input is LOW, SY100S834L functions as a divide by 2, VCC FSEL by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by CLK Q1 4 clock generation chip. This latter feature will increase the clock frequency by two folds. /Q0 /Q1 /CLK The common enable (/EN) is synchronous so that the internal dividers will only be enabled/disabled when the VCC VBB internal clock is already in the low state. This avoids any chance of generating a runt clock pulse on the MR Q2 internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal /Q2 VEE runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S834Ls in a system. 2020 Microchip Technology Inc. DS20006353A-page 1SY100S834L 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PECL Power Supply Voltage (V ) ( Note 1).............................................................................................................. +8V CC NECL Power Supply Voltage (V ) (Note 2) .............................................................................................................. 8V EE PECL Mode Input Voltage (V ) ( Note 3) ................................................................................................................... +6V IN NECL Mode Input Voltage (V ) (Note 4) ................................................................................................................... 6V IN Continuous Output Current (I ).......................................................................................................................... 50 mA OUT Surge Output Current (I ) ................................................................................................................................ 100 mA OUT Notice: Stresses above those listed under Absolute Maximum ratings may cause permanent damage to the fect device reliability. device. Exposure to maximum rating conditions for extended periods may af = 0V. Note 1: V EE = 0V. 2: V CC = 0V, V V . 3: V EE IN CC = 0V, V V . 4: V CC IN EE DC ELECTRICAL CHARACTERISTICS ( Note 1) Electrical Characteristics: V = 3.0V to 3.8V V = 0V or V = 3.8V to 3.0V V = 0V T = 40C to +85C, CC EE EE CC A unless otherwise stated. Parameter Symbol Min. Typ. Max. Units Conditions 49 T = 40C to +25C A Power Supply Current I mA EE = +85C 54 T A V 1.085 V 1.005 V 0.88 T = 40C Output High Voltage CC CC CC A V V OH ( Note 2) 1.025 V 0.955 V 0.88 T = 0C to +85C V CC CC CC A V 1.830 V 1.695 V 1.555 T = 40C Output Low Voltage CC CC CC A V V OL (Note 2) 1.810 V 1.705 V 1.620 T = 0C to +85C V CC CC CC A Input High Voltage (Single V V 1.165 V 0.880 V IH CC CC Ended) Input Low Voltage (Single V V 1.810 V 1.475 V IL CC CC Ended) V 1.38 V 1.26 V Output Reference Voltage V BB CC CC V 1.3 V 0.4 T = 40C Common Mode Range CC CC A V V IHCMR (Note 3) 1.4 V 0.4 T = 0C to +85C V CC CC A 150 A Input High Current I IH 0.5 A V = V (Min) Input Low Current I IL IN IL Note 1: Devices are designed to meet the DC specifications shown in the above table after thermal equilibration The circuit is in a test socket or mounted on a printed circuit board and transverse has been established. airflow greater than 500 lfpm is maintained 2: Outputs are terminated through a 50 resistor to V 2.0V. CC 3: The CMR range is referenced to the most positive side of the differential input voltage. Normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between 250 mV and 1V. DS20006353A-page 2 2020 Microchip Technology Inc.