SY58012U 5 GHz 1:2 LVPECL Fanout Buffer/Translator with Internal Input Termination Features General Description Precision 1:2, 800 mV LVPECL Fanout Buffer The SY58012U is a 2.5V/3.3V precision, high-speed, fully differential 1:2 LVPECL fanout buffer. Optimized to Guaranteed AC Performance over Temperature provide two identical output copies with less than 15 ps and Voltage: of skew, the SY58012U can process clock signals as -> 5 GHz f (Clock) MAX fast as 5 GHz or 5 Gbps data. -<11 0 ps Rise/Fall Time The differential input includes Microchips unique, 3-pin - <260 ps Propagation Delay input termination architecture that interfaces to - <15 ps Max Skew LVPECL, LVDS or CML differential signals, Low Jitter Design: (AC-coupled or DC-coupled) as small as 100 mV -6 0 fs Phase Jitter without any level-shifting or termination resistor RMS networks in the signal path. For AC-coupled input Accepts an Input Signal as Low as 100 mV interface applications, an on-board output reference Unique Input Termination and VT Pin Accepts DC- voltage (V ) is provided to bias the VT pin. The and AC-Coupled Differential Inputs (LVPECL, REF-AC outputs are 100k LVPECL compatible, with extremely LVDS and CML) fast rise/fall times guaranteed to be less than 110 ps. 800 mV (100k) LVPECL Output Swing The SY58012U operates from a 2.5V 5% supply or 2.5V 5% or 3.3V 10% Power Supply Operation 3.3V 10% supply and is guaranteed over the full Industrial Temperature Range: 40C to +85C industrial temperature range (40C to +85C). For Available in a 16-Lead 3 mm x 3 mm QFN applications that require faster rise/fall times, or greater Package bandwidth, consider the SY58013U 1:2 fanout buf fer with 400 mV output swing, or the SY58011U 1:2 CML Applications (400mV) fanout buffer. The SY58012U is part of All SONET and GigE Clock Distribution Microchips high-speed, Precision Edge product line. Fibre Channel Clock and Data Distribution Backplane Distribution Package Type High-End, Low Skew, Multiprocessor SY58012U Synchronous Clock Distribution 3 mm x 3 mm QFN-16 (M) (Top View) 16 15 14 13 IN 1 12 Q0 VT 2 /Q0 11 3 10 /Q1 VREF-AC 4 9 /IN Q1 5 6 7 8 2020 Microchip Technology Inc. 1DS20006319B-page VCC VCC GND GND GND GND VCC VCCSY58012U Functional Block Diagram Q0 IN /Q0 50 VT 50 /IN Q1 /Q1 -AC VREF 2DS20006319B-page 2020 Microchip Technology Inc.