Precision Edge 6GHz, 1:6 CML FANOUT BUFFER SY58034U Micrel, Inc. Precision Edge WITH 2:1 MUX INPUT AND SY58034U INTERNAL I/O TERMINATION FEATURES Provides six ultra-low skew copies of the selected input Precision Edge 2:1 MUX input included for clock switchover applications DESCRIPTION Guaranteed AC performance over temperature and voltage: The SY58034U is a 2.5V/3.3V precision, high-speed 1:6 Clock frequency range: DC to > 6GHz fanout buffer capable of handling clocks up to 6GHz. A <290ps IN-to-OUT t differential 2:1 MUX input is included for redundant clock pd <60ps t / t times switchover applications. r f <20ps skew (output-to-output) The differential input includes Micrels unique, 3-pin input Unique input isolation design minimizes crosstalk termination architecture that allows the device to interface to any differential signal (AC- or DC-coupled) as small as Ultra low-jitter design: 100mV without any level shifting or termination resistor 60fs RMS phase jitter networks in the signal path. The outputs are 50 source <0.7ps crosstalk-induced jitter RMS terminated CML, with extremely fast rise/fall times Low supply voltage operation: 2.5V and 3.3V guaranteed to be less than 60ps. Unique input termination and VT pin accepts DC- The SY58034U operates from a 2.5V 5% supply or a coupled and AC-coupled inputs (CML, PECL, LVDS) 3.3V 10% supply and is guaranteed over the full industrial Internal 50 output source termination temperature range of 40C to +85C. For applications that 400mV CML output swing require LVPECL outputs, consider the SY58035U or SY58036U Multiplexers. The SY58034U is part of Micrels 40C to +85C temperature range high-speed, Precision Edge product line. Available in 32-pin (5mm x 5mm) QFN package All support documentation can be found on Micrels web site at www.micrel.com. FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Redundant clock distribution 1:6 Fanout All SONET/SDH clock distribution Q0 All Fibre Channel distribution /Q0 All Gigabit Ethernet clock distribution 2:1 MUX IN0 Q1 50 /Q1 V 0 T0 50 /IN0 Q2 V REF-AC0 MUX /Q2 IN1 50 Q3 1 S V T1 /Q3 50 /IN1 Q4 V REF-AC1 /Q4 SEL (TTL/CMOS) Q5 /Q5 Precision Edge is a registered trademark of Micrel, Inc. Rev.: E Amendment: /0 M9999-082707 Issue Date: August 2007 1 hbwhelp micrel.com or (408) 955-1690Precision Edge SY58034U Micrel, Inc. PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish 1 24 IN0 GND 23 VT0 2 VCC SY58034UMG QFN-32 Industrial SY58034U with NiPdAu VREF-AC0 3 22 Q2 Pb-free bar-line indicator Pb-Free 4 21 /IN0 /Q2 (2) IN1 5 20 SY58034UMGTR QFN-32 Industrial SY58034U with NiPdAu Q3 6 19 VT1 /Q3 Pb-free bar-line indicator Pb-Free 7 18 VREF-AC1 VCC Notes: /IN1 8 GND 17 9 10 11 12 13 14 15 16 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin QFN PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 4 IN0, /IN0 Differential Input: These input pairs are the differential signal inputs to the device. These 5, 8 IN1, /IN1 inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the Input Interface Applications section for more details. 2, 6 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See Input Interface Applications section for more details. 31 SEL This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. The MUX select switchover function is asynchronous. 10 NC No connect. 11, 16, 18, VCC Positive Power Supply: Bypass with 0.1F 0.01F low ESR capacitors and place as 23, 25, 30 close to the VCC pins as possible. 29, 28 Q0, /Q0, Differential Outputs: These CML output pairs are low skew output copies of the selected 27, 26 Q1, /Q1, input. The output stage is optimized to deliver a 400mV swing (single-ended) into 50. 22, 21 Q2, /Q2, Each output includes a 50 source-termination resistor, thus minimizing any return 20, 19 Q3, /Q3, reflections. Unused output pins may be left floating. Please refer to the Truth Table 15, 14 Q4, /Q4, for details. 13, 12 Q5, /Q5 9, 17, 24, 32 GND, Ground. Ground pin and exposed pad must be connected to the same ground plane. Exposed Pad 3, 7 VREF-AC0, Reference Voltage: These output biases to V 1.2V. It is used for AC-coupling inputs CC VREF-AC1 (IN, /IN). Connect V directly to the VT pin. Bypass with 0.01F low ESR capacitor to REF-AC V . See Input Interface Applications section. Maximum sink/source current is 1.5mA. CC Due to the limited capability, the VREF-AC pin is only intended to drive its respective VT pin. TRUTH TABLE SEL 0 IN0 Input Selected 1 IN1 Input Selected M9999-082707 2 hbwhelp micrel.com or (408) 955-1690 GND GND NC SEL VCC VCC /Q5 Q0 Q5 /Q0 /Q4 Q1 Q4 /Q1 VCC VCC