Precision Edge 6GHz, 1:6 400mV LVPECL FANOUT SY58036U Micrel, Inc. Precision Edge BUFFER WITH 2:1 MUX INPUT SY58036U AND INTERNAL TERMINATION FEATURES Provides six ultra-low skew copies of the selected input Precision Edge 2:1 MUX input included for clock switchover DESCRIPTION applications Guaranteed AC performance over temperature and The SY58036U is a 2.5V/3.3V precision, high-speed, voltage: 1:6 fanout buffer capable of handling clocks up to 6GHz. Clock frequency range: DC to > 6GHz A differential 2:1 MUX input is included for redundant clock <300ps IN-to-OUT t pd switchover applications. <80ps t / t times r f The differential input includes Micrels unique, 3-pin input <20ps skew (output-to-output) termination architecture that allows the device to interface Ultra-low jitter design: to any differential signal (AC- or DC-coupled) as small as 50fs phase jitter (typ) RMS 100mV without any level shifting or termination resistor Low supply voltage operation: 2.5V and 3.3V networks in the signal path. The outputs are 400mV LVPECL (100K temperature compensated), with extremely fast rise/ Unique input termination and VT pin accepts DC- fall times guaranteed to be less than 80ps. coupled and AC-coupled inputs (CML, PECL, LVDS) The SY58036U operates from a 2.5V 5% supply or a Unique input isolation design minimizes crosstalk 3.3V 10% supply and is guaranteed over the full industrial 400mV LVPECL (100K compatible) output swing temperature range of 40C to +85C. For applications that 40C to +85C temperature range require CML outputs, consider the SY58034U or for 800mV Available in 32-pin (5mm x 5mm) MLF package LVPECL outputs the SY58035U. The SY58036U is part of Micrels high-speed, Precision Edge product line. All support documentation can be found on Micrels web site at www.micrel.com. APPLICATIONS FUNCTIONAL BLOCK DIAGRAM Redundant clock distribution 1:6 Fanout All SONET/SDH clock distribution Q0 All Fibre Channel distribution /Q0 All Gigabit Ethernet clock distribution 2:1 Mux IN0 Q1 50 /Q1 V 0 T0 50 /IN0 Q2 V REF-AC0 Mux /Q2 IN1 50 Q3 1 S V T1 /Q3 50 /IN1 Q4 V REF-AC1 /Q4 SEL (TTL/CMOS) Q5 /Q5 United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. Rev.: F Amendment: /0 M9999-073010 1 Issue Date: July 2010 hbwhelp micrel.com or (408) 955-1690 Precision Edge SY58036U Micrel, Inc. PACKAGE/ORDERING INFORMATION (1) Ordering Information Package Operating Package Lead 32 31 30 29 28 27 26 25 Part Number Type Range Marking Finish 1 24 IN0 GND SY58036UMI MLF-32 Industrial SY58036U Sn-Pb VT0 2 23 VCC (2) VREF-AC0 3 22 Q2 SY58036UMITR MLF-32 Industrial SY58036U Sn-Pb /IN0 4 21 /Q2 SY58036UMG(3) MLF-32 Industrial SY58036U with NiPdAu 5 20 IN1 Q3 Pb-Free bar-line indicator Pb-Free 6 19 VT1 /Q3 VREF-AC1 7 18 VCC (2, 3) SY58036UMGTR MLF-32 Industrial SY58036U with NiPdAu /IN1 8 17 GND Pb-Free bar-line indicator Pb-Free 9 10 11 12 13 14 15 16 Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC electricals only. A 2. Tape and Reel. 32-Pin MLF (MLF-32) 3. Pb-Free package recommended for new designs. PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 4 IN0, /IN0 Differential Input: These input pairs are the differential signal inputs to the device. These 5, 8 IN1, /IN1 inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the Input Interface Applications section for more details. 2, 6 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See Input Interface Applications section for more details. 31 SEL This single-ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. The MUX select switchover function is asynchronous. 10 NC No connect. 11, 16, 18, VCC Positive Power Supply: Bypass with 0.1F 0.01F low ESR capacitors and place as 23, 25, 30 close to the VCC pins as possible. 29, 28 Q0, /Q0, Differential Outputs: These 100K (temperature compensated) LVPECL output pairs are 27, 26 Q1, /Q1, low skew copies of the selected input. Please refer to the Truth Table for details. 22, 21 Q2, /Q2, 20, 19 Q3, /Q3, 15, 14 Q4, /Q4, 13, 12 Q5, /Q5 9, 17, 24, 32 GND, Ground. Ground pin and exposed pad must be connected to the same ground plane. Exposed Pad 3, 7 VREF-AC0 Reference Voltage: These output biases to V 1.2V. It is used for AC-coupling inputs CC VREF-AC1 (IN, /IN). Connect V directly to the VT pin. Bypass with 0.01F low ESR capacitor to REF-AC V . See Input Interface Applications section. Maximum sink/source current is 1.5mA. CC Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. TRUTH TABLE SEL 0 IN0 Input Selected 1 IN1 Input Selected M9999-073010 2 hbwhelp micrel.com or (408) 955-1690 GND GND NC SEL VCC VCC /Q5 Q0 Q5 /Q0 /Q4 Q1 Q4 /Q1 VCC VCC