SY58051AU Ultra-Precision CML AnyGate with Internal Input and Output Termination Revision 1.0 General Description The SY58051AU is an ultra-fast, low jitter universal logic Precision Edge gate with a guaranteed maximum data or clock throughput of 10.7Gbps or 8GHz, respectively. This AnyGate Features differential logic device will produce many logic functions of two Boolean variables, such as AND, NAND, OR, NOR, Three matched-delay input pairs provide any logic DELAY, or NEGATION. function: AND, NAND, OR, NOR The SY58051AU differential inputs include a unique Guaranteed AC performance over temperature and internal termination design that allows access to the voltage: termination network throughout a VT pin. This feature DC to >10.7Gbps data rate throughput allows the device to easily interface to different logic DC to >8GHz clock f MAX standards, both AC- and DC-coupled, without external <160ps Any In-to-Out t pd resistor-bias and termination networks. The result is a 20ps typical t /t clean, stub-free, low-jitter interface solution. The r f differential CML output is optimized for environments with Ultra-low jitter design: internal 50 source termination and a 400mV output 0.2ps typical random jitter (data) RMS swing. 2ps typical deterministic jitter (data) PP The SY58051AU operates from a 2.5V or 3.3V supply and 5ps typical total jitter (clock) PP is guaranteed over the full industrial temperature range of 46fs typical additive phase jitter (clock) RMS 40C to +85C. The SY58051AU is part of Micrels Unique input termination and VT pin accepts AC- and Precision Edge product family. DC-coupled inputs (CML, PECL) Datasheets and support documentation are available on Internal 50 output source termination Micrels web site at: www.micrel.com. Typical 400mV CML output swing (R = 50) L Internal 50 input termination Functional Block Diagram Power supply 2.5V 5% or 3.3V 10% 40C to +85C industrial temperature range Available in a 16-pin 3mm 3mm QFN package Applications Data communciation systems OC-192, OC-192+FEC data-to-clock All SONETOC-3 OC-768 applications Fibre Channel Gigabit Ethernet ATE Test and measurement AnyGate and Precision Edge are registered trademarks of Micrel, Inc. Micrel Inc. 2180 Fortune Drive S an Jose, CA 95131 USA tel +1 (408) 94-04800 fax + 1 (408) 47-41000 Micrel, Inc. SY58051AU Ordering Information Part Number Package Type Temperature Range Package Marking Lead Finish 051A with (1) SY58051AUMG Pb-Free QFN-16 Industrial NiPdAu Pb-Free Pb-Free bar-line indicator 051A with (1, 2) SY58051AUMG TR Pb-Free QFN-16 Industrial NiPdAu Pb-Free Pb-Free bar-line indicator Notes: 1. Pb-Free package recommended for new designs. 2. Tape and Reel Pin Configuration 16-Pin QFN Pin Description Pin Number Pin Name Pin Function Input termination center tap: Each of the two inputs (A, /A) terminates to this pin through a 50 1 VTA resistor. The VTA pin provides a center-tap to a termination network for maximum interface flexibility. See the Input Interface Applications section for more details. Differential input: These input pairs are the two data inputs to the device. Each pin of a pair (A, /A) 15, 16 A, /A and (B, /B) internally terminates to the VTA or VTB pin to 50. Note that these inputs will default 2, 3 B, /B to an indeterminate state if left open. See the Input Interface Applications section for more details. Input termination center tap: Each of the two inputs (B, /B) terminates to this pin through a 50 4 VTB resistor. The VTB pin provides a center-tap to a termination network for maximum interface flexibility. See the Input Interface Applications section for more details. Differential input: This input pair is the select input to the device. Each pin of this pair internally 5, 6 S, /S terminates to the VTS pin to 50. Note that this input will default to an indeterminate state if left open. See the Input Interface Applications section for more details. Input termination center tap: Each of the two inputs (S, /S) terminates to this pin. The VTS pin 7 VTS provides a center-tap to a termination network for maximum interface flexibility. 8, 13 VCC Positive power supply. Bypass with 0.1F0.01F low ESR capacitors. Differential output: This CML output pair is the output of the device. It is a logic function of the A, 12, 9 Q, /Q B, and S inputs. See the Truth Tables for details. 10, 11, 14 GND Ground. Exposed pad must be connected to the same potential as GND pin. Revision 1.0 January 28, 2014 2 hbwhelp micrel.com or (408) 955-1690