SY58603U 4.25Gbps Precision CML Buffer with Internal Termination and Fail Safe Input General Description The SY58603U is a 2.5/3.3V, high-speed, fully Precision Edge differential CML buffer optimized to provide less than 10ps total jitter. The SY58603U can process clock Features pp signals as fast as 2.5GHz or data patterns up to Precision 400mV CML buffer 4.25Gbps. Guaranteed AC performance over temperature and The differential input includes Micrels unique, 3-pin voltage: input termination architecture that interfaces to LVPECL, DC-to >4.25Gbps throughput LVDS or CML differential signals, (AC-coupled or DC- <300ps propagation delay (IN-to-Q) coupled) as small as 100mV (200mV ) without any pp level-shifting or termination resistor networks in the <85ps rise/fall times signal path. For AC-coupled input interface applications, Fail Safe Input an integrated voltage reference (V ) is provided to REF-AC Prevents output from oscillating when input is bias the V pin. The output is 400mV CML, with T invalid extremely fast rise/fall times guaranteed to be less than Ultra-low jitter design 85ps. <1ps cycle-to-cycle jitter RMS The SY58603U operates from a 2.5V 5% supply or <10ps total jitter PP 3.3V 10% supply and is guaranteed over the full industrial temperature range (40C to +85C). For <1ps random jitter RMS applications that require LVPECL or LVDS outputs, <10ps deterministic jitter PP consider the SY58604U and SY58605U, buffers with High-speed CML output 800mV and 325mV output swings respectively. The 2.5V 5% or 3.3V 10% power supply operation SY58603U is part of Micrels high-speed, Precision Industrial temperature range: 40C to +85C Edge product line. Available in 8-pin (2mm x 2mm) DFN package Data sheets and support documentation can be found on Micrels web site at: www.micrel.com. Applications Data Distribution: OC-48, OC-48+FEC, XAUI Functional Block Diagram Backplane Buffering SONET clock or data distribution Fibre Channel clock or data distribution Gigabit Ethernet clock or data distribution Markets Storage ATE Test and measurement Enterprise networking equipment High-end servers Access Metro area network equipment United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY58603U (1) Ordering Information Part Number Package Operating Package Marking Lead Type Range Finish SY58603UMG DFN-8 Industrial 603 with Pb-Free NiPdAu bar-line indicator Pb-Free (2) SY58603UMGTR DFN-8 Industrial 603 with Pb-Free NiPdAu bar-line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. Pin Configuration 8-Pin DFN Pin Description Pin Number Pin Name Pin Function 1, 4 IN, /IN Differential Input: This input pair is the differential signal input to the device. Input accepts DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of this pair internally terminates with 50 to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See Input Interface Applications section for more details. 2 VT Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See Input Interface Applications section. 3 VREF-AC Reference Voltage: This output biases to V 1.2V. It is used for AC-coupling input CC IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR capacitor to VCC. Maximum sink/source current is 1.5mA. Please refer to the Input Interface Applications section for more details. 5 GND Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pin. Exposed pad 6, 7 /Q, Q CML Differential Output Pair: Differential buffered output copy of the input signal. The output swing is typically 400mV. See CML Output Termination section. 8 VCC Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the V pin as possible. CC August 2007 2 M9999-082707-B hbwhelp micrel.com or (408) 955-1690