SY89645L Precision Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer General Description The SY89645L is a 3.3V, fully differential, low skew, 1:4 LVDS fanout buffer that accepts LVTTL or LVCMOS Precision Edge inputs. It is capable of processing clock signals as fast as 650MHz. The LVDS signals are optimized to provide less Features than 40ps of output skew. The single-ended input takes a 3.3V LVTTL or LVCMOS, Four identical LVDS outputs with a signal swing as small as 1.2V. The outputs are CLKIN accepts LVCMOS or LVTTL input levels 280mV LVDS, with fast rise and fall times, guaranteed to Maximum output frequency: 650MHz be less than 400ps. Translates LVCMOS/LVTTL input signals to LVDS levels The SY89645L operates from a 3.3V + 5% power supply <40ps output-to-output skew and is guaranteed over the full industrial temperature range (40C to +85C). The SY89645L is part of Micrels <3ns propagation delay Precision Edge product line. <400ps rise/fall times Data sheets and support documentation can be found on 3.3V 5% operating supply Micrels web site at: www.micrel.com. Industrial temperature range: 40C to +85C Available in 20-pin TSSOP Block Diagram Applications Communications High-performance computing Clock and data distribution Markets Datacom Telecom Storage ATE Test and Measurement Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. SY89645L Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish SY89645LK4G with NiPdAu SY89645LK4G K4-20-1 Industrial Pb-Free bar-line indicator Pb-Free (2) SY89645LK4G with NiPdAu SY89645LK4GTR K4-20-1 Industrial Pb-Free bar-line indicator Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at T = 25C, DC Electricals only. A 2. Tape and Reel. Pin Configuration 20-Pin TSSOP (K4-20-1) Pin Description Pin Number Pin Name Pin Function 1, 9, 13 GND Power Supply Ground. Clock Enable. When LOW, Q outputs are forced low, /Q outputs are forced high. The synchronous nature of the enable function forces the output clocks to enable or disable following a rising and a 2 CLK EN falling edge of the input clock. When HIGH, clock outputs follow input clock. Internal 50k pull-up resistor. V = V /2. See Clock Enable (CLK EN) Description section. TH CC 3, 5, 6, 7, 8 NC No Connect. LVCMOS/LVTTL Clock Input. This is the input to the device. Input accepts single-ended input signals 4 CLKIN as small as 1.2V. V = V /2. Internal 50k pull-down resistor. TH CC Positive Supply Pins. Connect to 3.3V supply, bypass with low ESR capacitors, as close to pins as 10, 18 VCC possible. 11, 12 /Q3, Q3 LVDS Differential Output Pairs: Differential buffered copies of the input signal. The output swing is 14, 15 /Q2, Q2 typically 280mV. Normally terminated with 100 across the output pairs (Q and /Q). See LVDS 16, 17 /Q1, Q1 Output Termination section. 19, 20 /Q0, Q0 M9999-060711 June 2011 3 hbwhelp micrel.com or (408) 955-1690