Supertex inc. TP2522 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description Low threshold (-2.4V max.) This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertexs High input impedance well-proven silicon-gate manufacturing process. This Low input capacitance (125pF max.) combination produces a device with the power handling Fast switching speeds capabilities of bipolar transistors and with the high input Low on-resistance impedance and positive temperature coefficient inherent Free from secondary breakdown in MOS devices. Characteristic of all MOS structures, this Low input and output leakage device is free from thermal runaway and thermally-induced secondary breakdown. Applications Logic level interfaces - ideal for TTL and CMOS Supertexs vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very Solid state relays low threshold voltage, high breakdown voltage, high input Battery operated systems impedance, low input capacitance, and fast switching speeds Photo voltaic drives are desired. Analog switches General purpose line drivers Telecom switches Ordering Information Product Summary R Part Number Package Option Packing V I DS(ON) GS(th) D(ON) BV /BV DSS DGS (max) (min) (max) TP2522N8-G TO-243AA (SOT-89) 2000/Reel -G denotes a lead (Pb)-free / RoHS compliant package. -220V 12 -2.4V -750mA Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. Pin Configuration Absolute Maximum Ratings DRAIN Parameter Value Drain-to-source voltage BV DSS Drain-to-gate voltage BV DGS SOURCE Gate-to-source voltage 20V DRAIN O O GATE Operating and storage temperature -55 C to +150 C Absolute Maximum Ratings are those values beyond which damage to the device TO-243AA (SOT-89) may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Product Marking Typical Thermal Resistance W = Code for week sealed TP5CW Package = Green Packaging ja O TO-243AA (SOT-89) 133 C/W Package may or may not include the following marks: Si or TO-243AA (SOT-89) Doc. DSFP-TP2522 Supertex inc. C081413 www.supertex.comTP2522 Thermal Characteristics Power Dissipation I I D D Package I I O DR DRM T = 25 C (continuous) (pulsed) A TO-243AA (SOT-89) -260mA -2.0A 1.6W -260mA -2.0A I (continuous) is limited by max rated T . D j Mounted on FR5 board, 25mm x 25mm x 1.57mm. Electrical Characteristics (T = 25C unless otherwise specified) A Sym Parameter Min Typ Max Units Conditions BV Drain-to-source breakdown voltage -220 - - V V = 0V, I = -2.0mA DSS GS D V Gate threshold voltage -1.0 - -2.4 V V = V , I = -1.0mA GS(th) GS DS D O V Change in V with temperature - - 4.5 mV/ C V = V , I = -1.0mA GS(th) GS(th) GS DS D I Gate body leakage - - -100 nA V = 20V, V = 0V GSS GS DS - -10 A V = 0V, V = Max Rating GS DS I Zero gate voltage drain current - DSS V = 0.8 Max Rating, DS - -1.0 mA V = 0V, T = 125C GS A -0.25 -0.7 - V = -4.5V, V = -25V GS DS I On-state drain current A D(ON) -0.75 -2.1 - V = -10V, V = -25V GS DS 10 15 V = -4.5V, I = -100mA Static drain-to-source on-state GS D R - DS(ON) resistance 8.0 12 V = -10V, I = -200mA GS D O R Change in R with temperature - - 1.7 %/ C V = -10V, I = -200mA DS(ON) DS(ON) GS D G Forward transconductance 100 250 - mmho V = -25V, I = -200mA FS DS D C Input capacitance - 75 125 ISS V = 0V, GS C Common source output capacitance - 20 85 pF V = -25V, OSS DS f = 1.0 MHz C Reverse transfer capacitance - 10 35 RSS t Turn-on delay time - - 10 d(ON) V = -25V, DD t Rise time - - 15 r ns I = -750mA, D t Turn-off delay time - - 20 d(OFF) R = 25 GEN t Fall time - - 15 f V Diode forward voltage drop - - -1.8 V V = 0V, I = -500mA SD GS SD t Reverse recovery time - 300 - ns V = 0V, I = -500mA rr GS SD Notes: O 1. All D.C. parameters 100% tested at 25 C unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V Pulse 10% Generator INPUT R 90% GEN -10V t t (ON) (OFF) D.U.T. t t t t d(ON) r d(OFF) f INPUT OUTPUT 0V 90% 90% R L OUTPUT 10% 10% VDD VDD Doc. DSFP-TP2522 Supertex inc. C081413 2 www.supertex.com