VS-705 Single Frequency VCSO Features Industry Standard Package, 5.0 x 7.5 x 2.5 mm th 5 Generation ASIC Technology for Ultra Low Jitter 120 fs-rms (fN = 622.08 MHz, 12 kHz to 20 MHz) 105 fs-rms (f = 622.08 MHz, 50 kHz to 80 MHz) N Output Frequencies from 122.88 MHz to 1.00 GHz Spurious Suppression, 90 dBc Typical 2.5V or 3.3V Supply Voltage LVPECL or LVDS Output Configurations Tri-State Output Select (OD, OS, OE) Compliant to EC RoHS Directive Pb Applications PLL circuits for Clock Smoothing and Frequency Translation Description Standard GR-253-CORE SONET / SDH ITU-T G.709/Y.1331 OTN (Optical Transport Network) IEEE 802.3ae 10 GbE (Gigabit Ethernet) INCITS 364-2003 10 GFC (Gigabit Fibre Channel) IEEE 802.3ba 40 GbE & 100 GbE ITU-T G.8261 Synchronous Ethernet IEEE 802.16 WiMax Description Vcc COutput Output The VS-705 is a Voltage Controlled SAW Oscillator that operates at the fundamental frequency of the internal SAW filter. The SAW filter is a high-Q Quartz device that enables the circuit to achieve low phase jitter performance over a wide SAW LVPECL operating temperature range. A divider circuit is deployed for LVDS output frequencies less than 491.52 MHz. The oscillator is housed in a hermetically sealed leadless surface mount package and offered on tape and reel. It has a tri-state Output 1 Select function that provides one of three conditions: Output X=1,2,4 X Disable, Output Set, or Output Enable. Vc OSelect Gnd Page 1 of 9 Rev: 25June2021 VS-705 Single Frequency VCSO Electrical Performance: 3.3V LV-PECL Parameter Symbol Minimum Typical Maximum Units Notes Frequency Nominal Frequency fN 120 1000 MHz 1,2,3 Absolute Pull Range APR 50 ppm 1,2,3,9 Linearity Lin % 2,4,9 7 Gain Transfer K +445 ppm/V 2,9 V Temperature Stability f ppm 1,7 STAB 100 Supply Voltage ( 10%) V 2.97 3.3 3.63 V 2,3 CC Current (Typical 50 Load) I 73 mA 3 CC Current (No Load) I 60 75 mA 3 CC Outputs Mid Level VCC-1.5 VCC-1.3 VCC-1.1 mV 2,3 Single Ended Swing 750 mV-pp 2,3 Differential Swing 1.5 V-pp 2,3 Current I 20 mA 7 OUT Rise Time t 180 250 ps-pp 6,7 R Fall Time t 180 250 ps-pp 6,7 F Symmetry SYM 45 50 55 % 2,3 Spurious Suppression 85 90 dBc 7 Jitter (>491.52 MHz to <1000.0 MHz) J 150 fs-rms 7,8 Jitter (>245.76 MHz to <491.52 MHz) 190 fs-rms 7,8 J Jitter (>122.88 MHz to <245.76 MHz) 280 fs-rms 7,8 J Control Voltage Input Impedance (Output Enabled) Z 123 7 C k Input Impedance (Output Disabled) ZC 472 7 k Modulation Bandwidth BW 200 kHz 7 T -40 +85 C 1,3 Operating Temperature OP Package Size 5.0 x 7.5 x 2.5 mm Mass 0.17 g 1. See Standard Frequencies and Ordering Information (Pg 8). 2. Parameters are tested with production test circuit (Pg 3). 3. Parameters are tested at ambient temperature with test limits guard-banded for specified operating temperature. 4. Measured as the maximum deviation from the best straight-line fit, per MIL-0-55310. 5. The Vc Model is described below (Fig 1). 6. Parameters are described with waveform diagram below (Fig 2). 7. Not tested in production, guaranteed by design, verified at qualification. 8. For Frequencies >491.52 MHz, Jitter is Integrated across 50 kHz to 80 MHz. For Frequencies <491.52 MHz, Jitter is Integrated across 12 kHz to 20 MHz. (Both per GR-253-CORE Issue3). 9. Tested with Vc = 0.3V to 3.0V. SYM = 100 x t / t A B Vcc=+2V t tF R Vcc-1.1V 123k Vc 80% + Vcc-1.3V 3pF 1.65V - 20% Vcc-1.5V t A t B Figure 1. Vc Model Output Enabled Figure 2. 10K LV-PECL Waveform Page 2 of 9 Rev: 25Jun2021