ZL38004QCG1 Microchip

ZL38004 Dedicated Voice Processor with Dual Channel Codec Data Sheet A full Design Manual is available to qualified August 2011 customers. To register, please send an email to Ordering Information VoiceProcessing Zarlink.com. ZL38004QCG1 100 Pin LQFP* Trays, Bake & Drypack Features ZL38004GGG2 96 Pin VFBGA* Trays, Bake & Drypack 100 MHz (200 MIPs) Zarlink voice processor with *Pb Free Matte Tin Butterfly hardware accelerator and -40 C to +85 C breakpoint/interrupt controller On-board Data (26 Kbytes), Instruction (24 Watchdog and 2 auxiliary timers Kbytes RAM and Boot (3 Kbytes) ROM 11 General Purpose Input/Output (GPIO) pins Dual ADCs with input buffer gain selection programmable to either 8 or 16 kHz sampling General purpose UART port Bootloadable for future Zarlink software upgrades Dual DACs with output sampling of 8, 16, 44.1 and 48 kHz and internal output driver External oscillator or crystal/ceramic resonator 2048 tap Filter co-processor shared across up to 1.2 V Core 3.3 V IO with 5 V-tolerant inputs 16 separate functions in 128 tap increments IEEE-1149.1 compatible JTAG port 2 Dual function Inter-IC Sound (I S) or Secondary TDM port Applications Primary PCM port supports TDM (ST BUS, GCI or McBSP framing) or SSI modes at bit rates of 128, Hands-free car kits 256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec Full duplex speaker-phone for digital telephone Separate slave (microcontroller) and master Echo cancellation for video conferences (Flash) SPI ports, maximum clock rate = 25 MHz Buffer OSCo IRQ 15:0 100 MHz MCLK CODEC 0 APLL OSC Instruction Interrupt OSCi ADC RAM PCM CLKi Controller DAC PCM LBCi 24K PCM P0 Clock DSP Bytes 5 Driver Core Chain JTAG / IRQ Buffer 3K Boot Timing CODEC 1:0 CODEC 1 ROM Bytes Generator Device Clocks ADC Data RAM DAC 5 IRQ Master IRQ / 27K SPI ButterFly Bytes Driver IRQ IRQ Hardware Accelerator 4 IRQ Slave 5 / PCM P0 SPI / 2 IRQ IRQ IRQ Watchdog APLL IRQ UART / IRQ 5 AUX Timer1 2 Filter 11 I S PCM P1 IRQ / MCLK GPIO Co-processor / AUX Timer2 IRQ Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006-2011, Zarlink Semiconductor Inc. All Rights Reserved.ZL38004 Data Sheet Intercom Systems Security Systems Change Summary Changes from March 2006 issue to August 2011 issue. Page, section, figure and table numbers refer to this current issue. Page Item Change 1 Ordering Information Added VFBGA package. 7 Package Drawing Updated 96L VFBGA package drawing. 1.0 Functional Description The ZL38004 is a hardware platform designed to support advanced acoustic echo canceller (with noise reduction) firmware applications available from Zarlink Semiconductor. These applications are resident in external memory and are down-loaded by the ZL38004 resident boot code during initialization. The firmware products and manuals available at the release of this data sheet are: ZLS38500: Acoustic Echo Canceller with Noise Reduction for Hands-Free Car Kits ZLS38501 Speakerphone. If these applications do not meet your requirements, please contract your local Zarlink Sales Office for the latest firmware releases. The ZL38004 Advanced Acoustic Echo Canceller with Noise Reduction platform integrates Zarlinks Voice Processor (ZVP) DSP Core with a number of internal peripherals. These peripherals include the following: Two independent CODECs Two PCM ports - ST BUS, GCI, McBSP or SSI operation 2 An I S interface port A 2048 tap Filter Co-processor Two Auxiliary Timers and a Watchdog Timer 11 GPIO pins A UART interface A Slave SPI port and a Master SPI port A timing block that supports master and slave operation An IEEE - 1149.1 compatible JTAG port The DSP Core can process up to four 8-bit audio channels, two 16-bit audio channels or two 8-bit and one 16-bit audio channel. These audio channels may originate and terminate with the CODECs, or be communicated to 2 and from the DSP Core through the PCM ports or the I S port. 2 Zarlink Semiconductor Inc.