ZL38012
Voice Processor with
Dual Narrow Band Codecs
Data Sheet
A full Design Manual is available to qualified September 2010
customers. To register, please send an email to
Ordering Information
VoiceProcessing@Zarlink.com.
ZL38012LDG1 56 Pin QFN*
*Pb Free Matte Tin
Features
-40 C to +85 C
100 MHz (200 MIPs) Zarlink voice processor with
hardware accelerator.
Bootloadable for future Zarlink software upgrades
Dual 8 kHz sampling ADCs with input buffer
External oscillator or crystal/ceramic resonator
gain selection
1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
Dual 8 kHz DACs with internal output driver
2
Dual function Inter-IC Sound (I S) port or TDM
Applications
Port
Hands-free car kits
PCM port supports TDM (ST BUS, GCI or McBSP
framing) or SSI modes at bit rates of 128, 256, 512,
Full duplex speaker-phone for digital telephone
1024, 2048, 4096, 8192 or 16384 Kb/sec
Echo cancellation for video conferences
Separate slave (microcontroller) and master
(Flash) SPI ports, maximum clock rate = 25 MHz Intercom Systems
5 General Purpose Input/Output (GPIO) pins Security Systems
General purpose UART port
OSCo
100 MHz MCLK
CODEC[0] APLL
OSC
Interrupt OSCi
Instruction
ADC
Controller
Memory
DAC
3K
ROM
Bytes
Driver
DSP
27K
Core
Timing CODEC[1:0]
CODEC[1] Bytes RAM
Generator
Device Clocks
ADC
Hardware
Data RAM
Accelerator
DAC
5
Master
/
SPI
24K
Filter
Driver Bytes
Co-processor
4
5 Slave
/
PCM
/
SPI
2
I S
2
UART
/
5
GPIO
/
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2010, Zarlink Semiconductor Inc. All Rights Reserved.ZL38012 Data Sheet
1.0 Functional Description
The ZL38012 is a hardware platform designed to support advanced acoustic echo canceller (with noise reduction)
firmware applications available from Zarlink Semiconductor. These applications are resident in external memory
and are down-loaded by the ZL38012 resident boot code during initialization.
The firmware products and manuals available at the release of this data sheet are: ZLS385xx: Acoustic Echo
Canceller with Noise Reduction for Hands-Free Car Kits. If these applications do not meet your requirements,
please contact your local Zarlink Sales Office for the latest firmware releases.
The ZL38012 Advanced Acoustic Echo Canceller with Noise Reduction platform integrates Zarlinks Voice
Processor (ZVP) DSP Core with a number of internal peripherals. These peripherals include the following:
Two independent CODECs
2
PCM ports - ST BUS, GCI, McBSP or SSI operation/ S interface port
A 2048 tap Filter Co-processor (LMS, FIR and FAP realizations)
Two Auxiliary Timers and a Watchdog Timer
5 GPIO pins
A UART interface
A Slave SPI port and a Master SPI port
A timing block that supports master and slave operation
An IEEE - 1149.1 compatible JTAG port
The DSP Core can process up to two 8-bit audio channels or two 16-bit audio channels. These audio channels may
originate and terminate with the CODECs, or be communicated to and from the DSP Core through the PCM/ the
2
I S port.
2.0 Core DSP Functional Block
The ZL38012 DSP Core functional block, illustrated in Figure 1, is made up of a DSP Core, Interrupt Controller,
Data RAM, Instruction RAM, BOOT ROM and a ButterFly Hardware Accelerator. This block controls the timing
(APLL and Timing Generator), peripheral interfaces and Filter Co-processor through a peripheral
address/data/control bus.
The ZL38012 implementation of DSP core and Filter Co-processor have been optimized to efficiently support voice
processing applications. These applications are described in detail in the Firmware Manuals associated with this
hardware platform.
3.0 Codec[1:0]
The ZL38012 has two 16-bit fully differential CODECs (CODEC 0/1) that meet G.712 requirements at 8 kHz
sampling, see Figure 2. The ADC path consists of input signal pins C0/1_ADCi+ and C0/1_ADCi- (buffer output
pins C0/1_BF0+ and C0/1_BFo-), which feed selectable Microphone Amplifier or Line Amplifier options. Once past
th
the buffer the analog signal goes through a low pass antialiasing filter and to a 4 order feed-forward Modulator
that produces a Pulse Density Modulated (PDM) signal. Next the PDM signal goes through a Low Pass Decimation
Filter and then is converted into a 16-bit parallel word that can be read by the ZL38012 DSP (ADCout[15:0], Figure
2).
The ZL38012 DSP will send 16-bit parallel word samples (DACin[15:0], Figure 2) to the DAC where they are
converted to serial data and passed through an interpolation filter followed by a digital Modulator. The
Modulator generates PDM data, which then passes through a 32-tap FIR reconstruction filter. The reconstructed
analog signal is then passed to a unity voltage gain differential output driver and to pins C0/1_DACo+ and
C0/1_DACo-.
2
Zarlink Semiconductor Inc.