ZL40200 Precision 1:2 LVPECL Fanout Buffer Data Sheet April 2014 Ordering Information Features ZL40200LDG1 16 Pin QFN Trays ZL40200LDF1 16 Pin QFN Tape and Reel Inputs/Outputs Matte Tin Accepts differential or single-ended input Package size: 3 x 3 mm LVPECL, LVDS, CML, HCSL, LVCMOS o o -40 C to +85 C Two precision LVPECL outputs Applications Operating frequency up to 750 MHz General purpose clock distribution Power Low jitter clock trees Options for 2.5 V or 3.3 V power supply Logic translation Core current consumption of 49 mA Clock and data signal restoration On-chip Low Drop Out (LDO) Regulator for superior Wired communications: OTN, SONET/SDH, GE, power supply rejection 10 GE, FC and 10G FC PCI Express generation 1/2/3 clock distribution Performance Wireless communications Ultra low additive jitter of 39 fs RMS High performance microprocessor clock distribution out0 p out0 n clk p Buffer clk n out1 p out1 n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2014, Microsemi Corporation. All Rights Reserved.ZL40200 Data Sheet Table of Contents Features . 1 Inputs/Outputs . 1 Power 1 Performance . 1 Applications . 1 Change Summary . 4 1.0 Package Description 5 2.0 Pin Description . 5 3.0 Functional Description 6 3.1 Clock Inputs . 6 3.2 Clock Outputs 11 3.3 Device Additive Jitter . 15 3.4 Power Supply 16 3.4.1 Sensitivity to power supply noise . 16 3.4.2 Power supply filtering 16 3.4.3 PCB layout considerations 16 4.0 AC and DC Electrical Characteristics . 17 5.0 Performance Characterization . 20 6.0 Typical Behavior 21 7.0 Package Thermal Characteristics 23 8.0 Mechanical Drawing . 24 2 Microsemi Corporation