EDB4432BBPA-1D-F-D Micron

168-Ball, Single-channel Mobile LPDDR2 SDRAM Features Mobile LPDDR2 SDRAM EDB4432BBPA, EDB8132B4PM, EDBM432B3PB, EDBM432B3PF, EDBA232B2PB, EDBA232B2PF Options Features V /V /V : 1.8V/1.2V/1.2V DD1 DD2 DDQ Ultra-low-voltage core and I/O power supplies Array configuration Frequency range 128 Meg x 32 (SDP) 533 MHz (data rate: 1066 Mb/s/pin) 256 Meg x 32 (DDP) 4n prefetch DDR architecture 384 Meg x 32 (3DP) 8 internal banks for concurrent operation 512 Meg x 32 (QDP) Multiplexed, double data rate, command/address Packaging inputs commands entered on each CK t/CK c 12mm x 12mm, 168-ball PoP FBGA package edge Operating temperature range Bidirectional/differential data strobe per byte of From 30C to +85C data (DQS t/DQS c) Programmable READ and WRITE latencies (RL/WL) Burst length: 4, 8 and 16 Per-bank refresh for concurrent operation Auto temperature-compensated self refresh (ATCSR) by built-in temperature sensor Partial-array self refresh (PASR) Deep power-down mode (DPD) Selectable output drive strength (DS) Clock-stop capability Lead-free (RoHS-compliant) and halogen-free packaging Table 1: Configuration Addressing Architecture 128 Meg x 32 256 Meg x 32 384 Meg x 32 512 Meg x 32 Density per package 4Gb 8Gb 12Gb 16Gb Die per package 1 2 3 4 Ranks (CS n) per channel 1 2 2 2 Die per rank CS0 n 1 1 2 2 CS1 n 0 1 1 2 Configuration per CS0 n 16 Meg x 32 x 8 16 Meg x 32 x 8 banks 32 Meg x 16 x 8 banks 32 Meg x 16 x 8 banks rank (CS n) banks x 2 x 2 CS1 n N/A 16 Meg x 32 x 8 banks 16 Meg x 32 x 8 banks 32 Meg x 16 x 8 banks x 2 Row addressing 16K A 13:0 16K A 13:0 16K A 13:0 16K A 13:0 Column CS0 n 1K A 9:0 1K A 9:0 2K A 10:0 2K A 10:0 addressing/CS n CS1 n N/A 1K A 9:0 1K A 9:0 2K A 10:0 PDF: 09005aef85c99ac2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 168b 12x12 4-16gb 2e0e lpddr2.pdf Rev. A 07/14 EN 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.168-Ball, Single-channel Mobile LPDDR2 SDRAM Features Table 2: Key Timing Parameters Speed Clock Rate Data Rate WRITE READ Grade (MHz) (Mb/s/pin) Latency Latency 1D 533 1066 4 8 Table 3: Part Number Description Part Total Package Ball Number Density Configuration Ranks Channels Size Pitch EDB4432BBPA-1D-F-R, 4Gb 128 Meg x 32 1 1 12mm x 12mm 0.50mm EDB4432BBPA-1D-F-D (0.80mm MAX height) EDB8132B4PM-1D-F-R, 8Gb 256 Meg x 32 2 1 12mm x 12mm 0.50mm EDB8132B4PM-1D-F-D (0.82mm MAX height) EDBM432B3PB-1D-F-R, 12Gb 384 Meg x 32 2 1 12mm x 12mm 0.50mm EDBM432B3PB-1D-F-D (0.90mm MAX height) EDBM432B3PF-1D-F-R, 12Gb 384 Meg x 32 2 1 12mm x 12mm 0.50mm EDBM432B3PF-1D-F-D (0.92mm MAX height) EDBA232B2PB-1D-F-R, 16Gb 512 Meg x 32 2 1 12mm x 12mm 0.50mm EDBA232B2PB-1D-F-D (1.00mm MAX height) EDBA232B2PF-1D-F-R, 16Gb 512 Meg x 32 2 1 12mm x 12mm 0.50mm EDBA232B2PF-1D-F-D (1.02mm MAX height) PDF: 09005aef85c99ac2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 168b 12x12 4-16gb 2e0e lpddr2.pdf Rev. A 07/14 EN 2014 Micron Technology, Inc. All rights reserved.