M25PX32-VZM6F Micron

M25PX32 32-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface Features SPI bus compatible serial interface 75 MHz (maximum) clock frequency 2.7 V to 3.6 V single supply voltage Dual input/output instructions resulting in an VFQFPN8 (MP) equivalent clock frequency of 150 MHz: 6 5 mm Dual Output Fast Read instruction Dual Input Fast Program instruction 32 Mbit Flash memory Uniform 4-Kbyte subsectors Uniform 64-Kbyte sectors SO8W (MW) Additional 64-byte user-lockable, one-time 208 mils programmable (OTP) area Erase capability Subsector (4-Kbyte) granularity Sector (64-Kbyte) granularity Bulk Erase (32 Mbit) in 34 s (typical) Write protections Software write protection applicable to SO16 (MF) every 64-Kbyte sector (volatile lock bit) 300 mils Hardware write protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2) Deep Power-down mode: 5 A (typical) Electronic signature JEDEC standard two-byte signature (7116h) Unique ID code (UID) with16 bytes read- TBGA24 (ZM) 6x8 mm only, available upon customer request More than 100 000 write cycles per sector More than 20 year data retention Packages RoHS compliant Automotive Certified Parts Available March 2009 Rev 10 1/68 www.numonyx.com 1Contents M25PX32 Contents 1 Description . 6 2 Signal descriptions 9 2.1 Serial Data output (DQ1) 9 2.2 Serial Data input (DQ0) . 9 2.3 Serial Clock (C) . 9 2.4 Chip Select (S) 9 2.5 Hold (HOLD) 9 2.6 Write Protect/Enhanced Program supply voltage (W/V ) 10 PP 2.7 V supply voltage 10 CC 2.8 V ground 10 SS 3 SPI modes 11 4 Operating features . 13 4.1 Page programming 13 4.2 Dual Input Fast Program . 13 4.3 Subsector Erase, Sector Erase and Bulk Erase 13 4.4 Polling during a Write, Program or Erase cycle 13 4.5 Active Power, Standby Power and Deep Power-down modes . 14 4.6 Status Register . 14 4.7 Protection modes . 15 4.7.1 Protocol-related protections 15 4.7.2 Specific hardware and software protection 16 4.8 Hold condition 18 5 Memory organization . 19 6 Instructions . 23 6.1 Write Enable (WREN) . 25 6.2 Write Disable (WRDI) 26 6.3 Read Identification (RDID) 27 2/68