MT40A1G16RC-062E:B Micron

16Gb: x4, x8, x16 DDR4 SDRAM Features DDR4 SDRAM MT40A4G4 MT40A2G8 MT40A1G16 1 Options Marking Features Configuration V = V = 1.2V 60mV DD DDQ 4 Gig x 4 4G4 V = 2.5V, 125mV, +250mV PP 2 Gig x 8 2G8 On-die, internal, adjustable V generation REFDQ 1 Gig x 16 1G16 1.2V pseudo open-drain I/O 78-ball FBGA package (Pb-free) x4, x8 T maximum up to 95C C 10mm x 11mm Rev. B VA 64ms, 8192-cycle refresh up to 85C 9mm x 11mm Rev. E JC 32ms, 8192-cycle refresh at >85C to 95C 96-ball FBGA package (Pb-free) x16 16 internal banks (x4, x8): 4 groups of 4 banks each 10mm x 13mm Rev. B RC 8 internal banks (x16): 2 groups of 4 banks each 9mm x 13mm Rev. E KD 8n-bit prefetch architecture Timing cycle time Programmable data strobe preambles 0.625ns CL = 22 (DDR4-3200) -062E Data strobe preamble training 0.682ns CL = 21 (DDR4-2933) -068 Command/Address latency (CAL) Operating temperature Multipurpose register READ and WRITE capability Commercial (0 T 95C) None C Write leveling Industrial (40 T 95C) IT C Self refresh mode Revision :B, :E Low-power auto self refresh (LPASR) 1. Not all options listed can be combined to Note: Temperature controlled refresh (TCR) define an offered product. Use the part Fine granularity refresh catalog search on 16Gb: x4, x8, x16 DDR4 SDRAM Features Table 2: Addressing Parameter 4096 Meg x 4 2048 Meg x 8 1024 Meg x 16 Number of bank groups 4 4 2 Bank group address BG 1:0 BG 1:0 BG0 Bank count per group 4 4 4 Bank address in bank group BA 1:0 BA 1:0 BA 1:0 Row addressing 256K (A 17:0 ) 128K (A 16:0 ) 128K (A 16:0 ) Column addressing 1K (A 9:0 ) 1K (A 9:0 ) 1K (A 9:0 ) 1 Page size 512B 1KB 2KB Note: 1. Page size is per bank, calculated as follows: COLBITS Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. CCM005-1406124318-10453 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 16gb ddr4 dram.pdf - Rev. G 08/2020 EN 2018 Micron Technology, Inc. All rights reserved.