4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Mobile LPDDR2 SDRAM MT42L256M16D1, MT42L128M32D1, MT42L256M32D2, MT42L128M64D2, MT42L512M32D4, MT42L192M64D3, MT42L256M64D4, MT42L384M32D3 Options Marking Features V : 1.2V L DD2 Ultra low-voltage core and I/O power supplies Configuration V = 1.141.30V DD2 32 Meg x 16 x 8 banks x 1 die 256M16 V /V = 1.141.30V DDCA DDQ 16 Meg x 32 x 8 banks x 1 die 128M32 V = 1.701.95V DD1 16 Meg x 32 x 8 banks x 2 die 256M32 Clock frequency range 1 (16 Meg x 32 x 8 banks) + 2 (32 384M32 53310 MHz (data rate range: 106620 Mb/s/pin) Meg x 16 x 8 banks) Four-bit prefetch DDR architecture 32 Meg x 16 x 8 banks x 4 die 512M32 Eight internal banks for concurrent operation 16 Meg x 32 x 8 banks x 2 die 128M64 Multiplexed, double data rate, command/address 16 Meg x 32 x 8 banks x 3 die 192M64 inputs commands entered on every CK edge 16 Meg x 32 x 8 banks x 4 die 256M64 Bidirectional/differential data strobe per byte of Device type data (DQS/DQS ) LPDDR2-S4, 1 die in package D1 Programmable READ and WRITE latencies (RL/WL) LPDDR2-S4, 2 die in package D2 Programmable burst lengths: 4, 8, or 16 LPDDR2-S4, 3 die in package D3 Per-bank refresh for concurrent operation LPDDR2-S4, 4 die in package D4 On-chip temperature sensor to control self refresh FBGA green package rate 134-ball FBGA (10mm x GU, GV Partial-array self refresh (PASR) 11.5mm) Deep power-down mode (DPD) 168-ball FBGA (12mm x 12mm) LF, LG Selectable output drive strength (DS) 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM, Clock stop capability LP RoHS-compliant, green packaging 220-ball FBGA (14mm x 14mm) LD, MP 240-ball FBGA (14mm x 14mm) MC 253-ball FBGA (11mm x 11mm) EU, EV Table 1: Key Timing Parameters Timing cycle time 1.875ns RL = 8 -18 Speed Clock Rate Data Rate t t 1 2.5ns RL = 6 -25 Grade (MHz) (Mb/s/pin) RL WL RCD/ RP 3.0ns RL = 5 -3 -18 533 1066 8 4 Typical Operating temperature range -25 400 800 6 3 Typical From 30C to +85C WT -3 333 667 5 2 Typical From 40C to +105C AT Revision :A t t 1. For Fast RCD/ RP, contact factory. Note: PDF: 09005aef84427aab Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 4gb mobile lpddr2 s4 u80m.pdf - Rev. O 08/13 EN 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.4Gb: x16, x32 Mobile LPDDR2 SDRAM S4 Features Table 2: Single Channel S4 Configuration Addressing Architecture 256 Meg x 16 128 Meg x 32 256 Meg x 32 384 Meg x 32 512 Meg x 32 Die CS0 32 Meg x 16 x 8 16 Meg x 32 x 8 16 Meg x 32 x 8 16 Meg x 32 x 8 32 Meg x 16 x 8 configuration banks banks banks banks banks CS1 n/a n/a 16 Meg x 32 x 8 32 Meg x 32 x 8 32 Meg x 16 x 8 banks banks banks Row addressing 16K (A 13:0 ) 16K (A 13:0 ) 16K (A 13:0 ) 16K (A 13:0 ) 16K (A 13:0 ) Column CS0 2K (A 10:0 ) 1K (A 9:0 ) 1K (A 9:0 ) 1K (A 9:0 ) 2K (A 10:0 ) addressing CS1 n/a n/a 1K (A 9:0 ) 2K (A 10:0 ) 2K (A 10:0 ) Number of die 1 1 2 3 4 Die per rank CS0 1 1 1 1 2 CS1 0 0 1 2 2 1 Ranks per channel 11222 Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins. Table 3: Dual Channel S4 Configuration Addressing Architecture 128 Meg x 64 192 Meg x 64 256 Meg x 64 Die configuration 16 Meg x 32 x 8 banks 16 Meg x 32 x 8 banks 16 Meg x 32 x 8 banks Row addressing 16K (A 13:0 ) 16K (A 13:0 ) 16K (A 13:0 ) Column addressing CS0 1K (A 9:0 ) 1K (A 9:0 ) 1K (A 9:0 ) CS1 n/a 1K (A 9:0 ) 1K (A 9:0 ) Number of die 2 3 4 Die per rank CS0 1 1 1 CS1 0 1 = Channel A 1 0 = Channel B 1 Ranks per channel Channel A 1 2 2 Channel B 1 1 2 Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins. PDF: 09005aef84427aab Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 4gb mobile lpddr2 s4 u80m.pdf - Rev. O 08/13 EN 2011 Micron Technology, Inc. All rights reserved.