2Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive LPDDR SDRAM MT46H128M16LF 32 Meg x 16 x 4 Banks MT46H64M32LF 16 Meg x 32 x 4 Banks MT46H128M32L2 16 Meg x 32 x 4 Banks x 2 MT46H256M32L4 32 Meg x 16 x 4 Banks x 4 Options Mark Features V /V DD DDQ V /V = 1.701.95V DD DDQ 1.8V/1.8V H Bidirectional data strobe per byte of data (DQS) Configuration Internal, pipelined double data rate (DDR) 256 Meg x 32 (32 Meg x 16 x 4 banks x 256M32 architecture two data accesses per clock cycle 4) 128 Meg x 32 (16 Meg x 32 x 4 banks x 128M32 Differential clock inputs (CK and CK ) 2) Commands entered on each positive CK edge 128 Meg x 16 (32 Meg x 16 x 4 banks) 128M16 DQS edge-aligned with data for READs center- 64 Meg x 32 (16 Meg x 32 x 4 banks) 64M32 aligned with data for WRITEs Addressing 4 internal banks for concurrent operation JEDEC-standard LF Data masks (DM) for masking write data one mask 2-die stack standard L2 per byte 4-die stack standard L4 Programmable burst lengths (BL): 2, 4, 8, or 16 Plasticgree package 60-ball VFBGA (8mm x 9mm) DD Concurrent auto precharge option is supported 90-ball VFBGA (8mm x 13mm) BQ Auto refresh and self refresh modes PoP (plasticgree package) 1.8V LVCMOS-compatible inputs 168-ball WFBGA DDP (12mm x KQ 2 Temperature-compensated self refresh (TCSR) 12mm) Partial-array self refresh (PASR) 168-ball TFBGA QDP (12mm x SA Deep power-down (DPD) 12mm) Timing cycle time Status read register (SRR) 4.8ns CL = 3 (208 MHz) -48 Selectable output drive strength (DS) 5ns CL = 3 (200 MHz) -5 Clock stop capability Special Options 64ms refresh 32ms for the automotive temperature None range Automotive (package-level burn-in) A Operating temperature range Table 1: Key Timing Parameters (CL = 3) From 40C to +85C IT 1 From 40C to +105C AT Speed Grade Clock Rate Access Time From 25C to +85C WT -48 208 MHz 4.8ns Design revision :C -5 200 MHz 5.0ns 1. Contact factory for availability. Notes: 2. Self refresh supported up to 85 C. Table 2: Configuration Addressing 2Gb Architecture 128 Meg x 16 64 Meg x 32 Configuration 32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks PDF: 09005aef8541eee0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 t89m auto lpddr.pdf - Rev. F 9/14 EN 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.2Gb: x16, x32 Automotive LPDDR SDRAM Features Table 2: Configuration Addressing 2Gb (Continued) Architecture 128 Meg x 16 64 Meg x 32 Refresh count 8K 8K Row addressing 16K A 13:0 16K A 13:0 Column addressing 2K A11, A 9:0 1K A 9:0 See Package Block Diagrams for descriptions of signal connections and die configurations for each respective ar- chitecture. Figure 1: 2Gb Mobile LPDDR Part Numbering MT 46 H 64M32 LF KQ -6 A IT :C Micron Technology Design Revision :C = Design generation Product Family 46 = Mobile LPDDR Operating Temperature IT = Industrial (40C to +85C) AT = Automotive (40C to +105C) Operating Voltage WT = Wireless (25C to +85C) H = 1.8/1.8V HC = 1.8/1.2V Special Options (Multiple processing codes are separated by a space and are listed in hierarchical order.) Configuration (depth, width) Blank = None 128 Meg x 16 A = Automotive 64 Meg x 32 128 Meg x 32 Speed Grade 256 Meg x 32 t -48 = 4.8ns CK t -5 = 5ns CK Addressing LF = JEDEC-standard addressing Package Codes L2 = 2-die stack standard addressing DD = 60-ball (8mm x 9mm) VFBGA, green L4 = 4-die stack standard addressing BQ = 90-ball (8mm x 13mm) VFBGA, green KQ = 168-ball (12mm x 12mm) WFBGA, green SA = 168-ball (12mm x 12mm) TFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef8541eee0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 t89m auto lpddr.pdf - Rev. F 9/14 EN 2013 Micron Technology, Inc. All rights reserved.