MT46V32M16P-5B:J TR Micron

512Mb: x4, x8, x16 DDR SDRAM Features Double Data Rate (DDR) SDRAM MT46V128M4 32 Meg x 4 x 4 banks MT46V64M8 16 Meg x 8 x 4 banks MT46V32M16 8 Meg x 16 x 4 banks Features Options Marking V = 2.5V 0.2V, V = 2.5V 0.2V Configuration DD DDQ 1 V = 2.6V 0.1V, V = 2.6V 0.1V (DDR400) 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 DD DDQ Bidirectional data strobe (DQS) transmitted/ 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 received with data, i.e., source-synchronous data Plastic package capture (x16 has two one per byte) 66-pin TSOP TG Internal, pipelined double-data-rate (DDR) 66-pin TSOP (Pb-free) P architecture two data accesses per clock cycle 2 60-ball FBGA (10mm x 12.5mm) FN Differential clock inputs (CK and CK ) 2 60-ball FBGA (10mm x 12.5mm) (Pb-free) BN Commands entered on each positive CK edge 3 60-ball FBGA (8mm x 12.5mm) CV DQS edge-aligned with data for READs center- 3 60-ball FBGA (8mm x 12.5mm) (Pb-free) CY aligned with data for WRITEs Timing cycle time DLL to align DQ and DQS transitions with CK 5ns CL = 3 (DDR400) -5B 2 Four internal banks for concurrent operation 6ns CL = 2.5 (DDR333) (FBGA only) -6 2 Data mask (DM) for masking write data 6ns CL = 2.5 (DDR333) (TSOP only) -6T Self refresh (x16 has two one per byte) Standard None Programmable burst lengths: 2, 4, or 8 Low-power self refresh L Auto refresh Temperature rating 64ms, 8192-cycle Commercial (0C to +70C) None Longer-lead TSOP for improved reliability (OCPL) Industrial (40C to +85C) IT 2.5V I/O (SSTL 2 compatible) Revision Concurrent auto precharge option is supported x4, x8, x16 :F t t t RAS lockout supported ( RAP = RCD) x4, x8, x16 :J Notes: 1. DDR400 devices operating at < DDR333 conditions can use V /V = 2.5V +0.2V. DD DDQ 2. Available only on Revision F. 3. Available only on Revision J. Table 1: Key Timing Parameters CL = CAS (READ) latency data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3 Clock Rate (MHz) Speed Data-Out Access DQSDQ Grade CL = 2 CL = 2.5 CL = 3 Window Window Skew -5B 133 167 200 1.6ns 0.70ns 0.40ns -6 133 167 n/a 2.1ns 0.70ns 0.40ns 6T 133 167 n/a 2.0ns 0.70ns 0.45ns -75E/-75Z 133 133 n/a 2.5ns 0.75ns 0.50ns -75 100 133 n/a 2.5ns 0.75ns 0.50ns PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mb DDR x4x8x16 D1.fm - 512Mb DDR: Rev. Q Core DDR Rev. E 7/11 EN 1 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Features Table 2: Addressing Parameter 128 Meg x 4 64 Meg x 8 32 Meg x 16 Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Refresh count 8K 8K 8K Row address 8K (A0A12) 8K (A0A12) 8K (A0A12) Bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Column address 4K (A0A9, A11, A12) 2K (A0-A9, A11) 1K (A0A9) Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) 1 Yes Yes Yes Yes Yes Yes -5B Yes Yes Yes Yes Yes -6 Yes Yes Yes Yes Yes -6T Yes Yes Yes Yes -75E Yes Yes Yes -75Z Yes Yes -75 -5B -6/-6T -75E -75Z -75 -75 Notes: 1. The -5B device is backward compatible with all slower speed grades. The voltage range of -5B device operating at slower speed grades is V = V = 2.5V 0.2V. DD DDQ Figure 1: 512Mb DDR SDRAM Part Numbers Example Part Number: MT46V32M16P-6T:F - : Sp. MT46V Configuration Package Speed Temp. Revision Op. Revision :F x4, x8, x16 :J x4, x8, x16 Configuration 128 Meg x 4 128M4 Operating Temp 64 Meg x 8 64M8 Commercial 32 Meg x 16 32M16 IT Industrial Package Special Options 400-mil TSOP TG Standard 400-mil TSOP (Pb-free) P L Low power 10mm x 12.5mm FBGA FN Speed Grade BN 10mm x 12.5mm FBGA (Pb-free) t -5B CK = 5ns, CL = 3 8mm x 12.5mm FBGA CV t 8mm x 12.5mm FBGA (Pb-free) CY -6 CK = 6ns, CL = 2.5 t -6T CK = 6ns, CL = 2.5 FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Microns Web site: www.micron.com. PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mb DDR x4x8x16 D1.fm - 512Mb DDR: Rev. Q Core DDR Rev. E 7/11 EN 2 2000 Micron Technology, Inc. All rights reserved.