512Mb: x8, x16 Automotive DDR SDRAM Features Automotive DDR SDRAM MT46V64M8 16 Meg x 8 x 4 banks MT46V32M16 8 Meg x 16 x 4 banks Features Options Marking V = 2.5V 0.2V, V = 2.5V 0.2V Configuration DD DDQ 1 V = 2.6V 0.1V, V = 2.6V 0.1V (DDR400) 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 DD DDQ Bidirectional data strobe (DQS) transmitted/ 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 Plastic package received with data, i.e., source-synchronous data 66-pin TSOP TG capture (x16 has two one per byte) 66-pin TSOP (Pb-free) P Internal, pipelined double-data-rate (DDR) 60-ball FBGA (8mm x 12.5mm) CV architecture two data accesses per clock cycle 60-ball FBGA (8mm x 12.5mm) CY Differential clock inputs (CK and CK ) (Pb-free) Commands entered on each positive CK edge Timing cycle time DQS edge-aligned with data for READs center- 5ns CL = 3 (DDR400) -5B aligned with data for WRITEs Self refresh DLL to align DQ and DQS transitions with CK Standard None Four internal banks for concurrent operation Low-power self refresh L Data mask (DM) for masking write data Temperature rating Industrial (40C to +85C) AIT (x16 has two one per byte) Automotive (40C to +105C) AAT Programmable burst lengths: 2, 4, or 8 Revision Auto refresh x8, x16 :J 64ms, 8192-cycle(AIT) 16ms, 8192-cycle (AAT) Notes: 1. DDR400 devices operating at < DDR333 con- Self refresh (not available on AAT devices) ditions can use V /V = 2.5V +0.2V. DD DDQ Longer-lead TSOP for improved reliability (OCPL) 2. Not all options listed can be combined to 2.5V I/O (SSTL 2 compatible) define an offered product. Use the Part Cata- Concurrent auto precharge option is supported log Search on www.micron.com for product t t t RAS lockout supported ( RAP = RCD) offerings and availability. AEC-Q100 PPAP Submission 8D Response time PDF:09005aef845d3bfc/Source: 09005aef845d3b9c Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mb DDR x4x8x16 D1.fm - 512Mb AIT-AAT DDR: Rev. B Core DDR Rev. C 7/18 EN 1 2000 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512Mb: x8, x16 Automotive DDR SDRAM Features Table 1: Key Timing Parameters CL = CAS (READ) latency data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5 and CL = 3 Clock Rate (MHz) Data-Out Speed Grade CL = 2 CL = 2.5 CL = 3 Window Access Window DQSDQ Skew -5B 133 167 200 1.6ns 0.70ns 0.40ns -6 133 167 n/a 2.1ns 0.70ns 0.40ns 6T 133 167 n/a 2.0ns 0.70ns 0.45ns -75E/-75Z 133 133 n/a 2.5ns 0.75ns 0.50ns -75 100 133 n/a 2.5ns 0.75ns 0.50ns Table 2: Addressing Parameter 64 Meg x 8 32 Meg x 16 Configuration 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Refresh count 8K 8K Row address 8K (A0A12) 8K (A0A12) Bank address 4 (BA0, BA1) 4 (BA0, BA1) Column address 2K (A0-A9, A11) 1K (A0A9) Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) 1 Yes Yes Yes Yes Yes Yes -5B Yes Yes Yes Yes Yes -6 Yes Yes Yes Yes Yes -6T Yes Yes Yes Yes -75E Yes Yes Yes -75Z Yes Yes -75 -5B -6/-6T -75E -75Z -75 -75 Notes: 1. The -5B device is backward compatible with all slower speed grades. The voltage range of -5B device operating at slower speed grades is V = V = 2.5V 0.2V. DD DDQ PDF:09005aef845d3bfc/Source: 09005aef845d3b9c Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mb DDR x4x8x16 D1.fm - 512Mb AIT-AAT DDR: Rev. B Core DDR Rev. B 7/11 EN 2 2000 Micron Technology, Inc. All rights reserved.