Hybrid Memory Cube HMC Gen2
HMC Memory Features
Hybrid Memory Cube HMC Gen2
MT43A4G40200 2GB 4H DRAM stack
Options Marking
HMC Memory Features
Configuration
V = 1.2V 0.06V
DDM
2GB cube (4Gb x 4H DRAM stack) 4G4
V = 2.5V 0.125V
CCP
BGA package (Pb-free)
2GB configuration
4-link (31mm x 31mm) 2GB NFA
128 memory banks
Operating temperature
Configured as 16 independent memory vaults
DRAM: (0C T 105C) None
J
Closed-page memory architecture
Logic: (0C T 110C) None
J
Built-in memory controller for each vault
PHY
Automatic refresh control over all temperatures
HMC Gen2 -S15
Internal ECC data correction
Logic revision 02
Advanced RAS features including data scrubbing
DRAM revision :A
Post-assembly repair capability
In-field repair for ultimate reliability
Description
Hybrid Memory Cube (HMC) is a single package con-
HMC Interface Features
taining four DRAM die and one logic die, all stacked
V = 0.9V
DD
together using through-silicon via (TSV) technology.
V , V , V = 1.2V
TT TR DDPLL
Within each cube, memory is organized vertically
V = 1.5 V
DDK
portions of each memory die are combined with the
10 Gb/s, 12.5 Gb/s, or 15 Gb/s SerDes I/O interface
corresponding portions of the other memory die in
Up to four 16-lane, full-duplex serialized links
the stack. Each grouping of memory partitions is com-
Half-width link (8-lane) configuration also sup-
bined with a corresponding section of the logic die,
ported
forming what is referred to as a vault.
Up to 160 GB/s bandwidth
Packet-based data/command interface
Specifications within this data sheet are compatible
Supports 16, 32, 48, 64, 80, 96, 112, and 128 byte da-
with the HMC Consortium Specification.
ta payloads per request
Cyclic redundancy check (CRC) error detection for
packets with automatic retry
Power management supported per link
Through-silicon via (TSV) technology
Built-in self-test (BIST)
JTAG interface (IEEE 1149.1-2001, 1149.6)
2 2
I C Interface (UM-10204 I C bus specification)
09005aef8462cb46 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
hmc_gen2.pdf - Rev. G 4/17 EN 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.Hybrid Memory Cube HMC Gen2
HMC Memory Features
Figure 1: HMC Part Numbers
Example Part Number: MT43A4G40100NFA-S15:A
- :
MT43A Config Package SerDes D Rev.
L Rev. PV
Configuration DRAM Die Revision
4Gb x 4 DRAM layers 4G4 Rev. A :A
Logic Design Revision SerDes Link Description
Revision 1 01 S15
15 Gb/s
Revision 2 02
Package Description (mm)
BGA, 4-link, 896-ball (31 x 31), 2GB NFA
Product Variations
Standard 00
09005aef8462cb46 Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
hmc_gen2.pdf - Rev. G 4/17 EN 2010 Micron Technology, Inc. All rights reserved.