MT47H64M16HW-3:H-TR Micron

1Gb: x4, x8, x16 DDR2 SDRAM Features DDR2 SDRAM MT47H256M4 32 Meg x 4 x 8 banks MT47H128M8 16 Meg x 8 x 8 banks MT47H64M16 8 Meg x 16 x 8 banks 1 Options Marking Features Configuration V = 1.8V 0.1V, V = 1.8V 0.1V DD DDQ 256 Meg x 4 (32 Meg x 4 x 8 banks) 256M4 JEDEC-standard 1.8V I/O (SSTL 18-compatible) 128 Meg x 8 (16 Meg x 8 x 8 banks) 128M8 Differential data strobe (DQS, DQS ) option 64 Meg x 16 (8 Meg x 16 x 8 banks) 64M16 FBGA package (Pb-free) x16 4n-bit prefetch architecture 84-ball FBGA (8mm x 12.5mm) Die HR Duplicate output strobe (RDQS) option for x8 Rev :H DLL to align DQ and DQS transitions with CK 84-ball FBGA (8mm x 12.5mm) Die NF 8 internal banks for concurrent operation Rev :M Programmable CAS latency (CL) FBGA package (Pb-free) x4, x8 Posted CAS additive latency (AL) 60-ball FBGA (8mm x 10mm) Die CF t Rev :H WRITE latency = READ latency - 1 CK 60-ball FBGA (8mm x 10mm) Die SH Selectable burst lengths (BL): 4 or 8 Rev :M Adjustable data-output drive strength FBGA package (lead solder) x16 64ms, 8192-cycle refresh 84-ball FBGA (8mm x 12.5mm) Die HW On-die termination (ODT) Rev :H Industrial temperature (IT) option FBGA package (lead solder) x4, x8 60-ball FBGA (8mm x 10mm) Die JN Automotive temperature (AT) option Rev :H RoHS-compliant Timing cycle time Supports JEDEC clock jitter specification 1.875ns CL = 7 (DDR2-1066) -187E 2.5ns CL = 5 (DDR2-800) -25E 3.0ns CL = 5 (DDR2-667) -3 Self refresh Standard None Low-power L Operating temperature 2 Commercial (0C T +85C) None C Industrial (40C T +95C IT C 40C T +85C) A Revision :H / :M 1. Not all options listed can be combined to Notes: define an offered product. Use the Part Catalog Search on www.micron.com for product offerings and availability. 2. For extended CT operating temperature see IDD Table 11 (page 32) Note 7. CCMTD-1725822587-9658 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 1GbDDR2.pdf Rev. AB 09/18 EN 2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.1Gb: x4, x8, x16 DDR2 SDRAM Features Table 1: Key Timing Parameters Data Rate (MT/s) t Speed Grade CL = 3 CL = 4 CL = 5 CL = 6 CL = 7 RC (ns) -187E 400 533 800 800 1066 54 -25E 400 533 800 800 n/a 55 -3 400 533 667 n/a n/a 55 Table 2: Addressing Parameter 256 Meg x 4 128 Meg x 8 64 Meg x 16 Configuration 32 Meg x 4 x 8 banks 16 Meg x 8 x 8 banks 8 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address A 13:0 (16K) A 13:0 (16K) A 12:0 (8K) Bank address BA 2:0 (8) BA 2:0 (8) BA 2:0 (8) Column address A 11, 9:0 (2K) A 9:0 (1K) A 9:0 (1K) Figure 1: 1Gb DDR2 Part Numbers Example Part Number: MT47H128M8SH-25E:M - : MT47H Configuration Package Speed Revision :H/:M Revision Configuration L Low power 256 Meg x 4 256M4 IT Industrial temperature 128 Meg x 8 128M8 64 Meg x 16 64M16 Speed Grade Package t -187E CK = 1.875ns, CL = 7 Pb-free t -25E CK = 2.5ns, CL = 5 84-ball 8mm x 12.5mm FBGA HR t -3 CK = 3ns, CL = 5 60-ball 8mm x 10.0mm FBGA CF 84-ball 8mm x 12.5mm FBGA NF 60-ball 8mm x 10.0mm FBGA SH Lead solder 84-ball 8mm x 12.5mm FBGA HW 60-ball 8mm x 10mm FBGA JN 1. Not all speeds and configurations are available in all packages. Note: FBGA Part Number System Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Microns Web site: