64Mb: x32 SDRAM
Features
SDR SDRAM
MT48LC2M32B2 512K x 32 x 4 Banks
Options Marking
Features
Configuration
PC100-compliant
2 Meg x 32 (512K x 32 x 4 banks) 2M32B2
Fully synchronous; all signals registered on positive
1
Plastic package OCPL
edge of system clock
86-pin TSOP II (400 mil) standard TG
Internal pipelined operation; column address can
86-pin TSOP II (400 mil) Pb-free P
be changed every clock cycle
90-ball VFBGA (8mm x 13mm) Pb- B5
Internal banks for hiding row access/precharge
free
Programmable burst lengths: 1, 2, 4, 8, or full page
Timing cycle time
Auto precharge, includes concurrent auto precharge
5ns (200 MHz) -5
and auto refresh modes
2
5.5ns (183 MHz) -55
Self refresh mode (not available on AT devices)
3
6ns (167 MHz) -6A
Auto refresh
2
6ns (167 MHz) -6
64ms, 4096-cycle refresh
2
7ns (143 MHz) -7
(commercial and industrial)
Operating temperature range
16ms, 4096-cycle refresh
Commercial (0C to +70C) None
(automotive)
Industrial (40C to +85C) IT
LVTTL-compatible inputs and outputs
4
Automotive (40C to +105C) AT
Single 3.3V 0.3V power supply
Revision :G/:J
Supports CAS latency (CL) of 1, 2, and 3
1. Off-center parting line.
Notes:
2. Available only on revision G.
3. Available only on revision J.
4. Contact Micron for availability.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Clock
t t t t
Speed Grade Frequency (MHz) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns)
-5 200 3-3-3 15 15 15
-55 183 3-3-3 16.5 16.5 16.5
-6A 167 3-3-3 18 18 18
-6 167 3-3-3 18 18 18
-7 143 3-3-3 20 20 21
PDF: 09005aef811ce1fe Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
64mb_x32_sdram.pdf - Rev. V 09/14 EN 1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.64Mb: x32 SDRAM
Features
Table 2: Address Table
Parameter 2 Meg x 32
Configuration 512K x 32 x 4 banks
Refresh count 4K
Row addressing 2K A[10:0]
Bank addressing 4 BA[1:0]
Column addressing 256 A[7:0]
Table 3: 64Mb (x32) SDR Part Numbering
Part Numbers Architecture Package
MT48LC2M32B2TG 2 Meg x 32 86-pin TSOP II
MT48LC2M32B2P 2 Meg x 32 86-pin TSOP II
1
MT48LC2M32B2B5 2 Meg x 32 90-ball VFBGA
Note: 1. FBGA Device Decoder: www.micron.com/decoder.
PDF: 09005aef811ce1fe Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
64mb_x32_sdram.pdf - Rev. V 09/14 EN 1999 Micron Technology, Inc. All rights reserved.