128Mb: x32 Automotive SDRAM Features Automotive SDR SDRAM MT48LC4M32B2 1 Meg x 32 x 4 Banks Options Marking Features Configuration PC100-compliant 4 Meg x 32 (1 Meg x 32 x 4 banks) 4M32B2 Fully synchronous all signals registered on positive 1 Package OCPL edge of system clock 86-pin TSOP II (400 mil) TG Internal pipelined operation column address can 86-pin TSOP II (400 mil) Pb-free P be changed every clock cycle 90-ball VFBGA (8mm x 13mm) F5 Internal banks for hiding row access/precharge 90-ball VFBGA (8mm x 13mm) Pb- B5 Programmable burst lengths: 1, 2, 4, 8, or full page free Auto precharge, includes concurrent auto precharge Timing (cycle time) and auto refresh modes 3 6ns (167 MHz) -6A Self refresh mode (not available on AT devices) 2 6ns (167 MHz) -6 Auto refresh 2 7ns (143 MHz) -7 64ms, 4096-cycle refresh (commercial and Revision :G/:L industrial) Special options 16ms, 4096-cycle refresh (automotive) 4 Automotive grade A LVTTL-compatible inputs and outputs Product longevity program X Single 3.3V 0.3V power supply Operating temperature range Supports CAS latency (CL) of 1, 2, and 3 Industrial (40C to +85C) IT AEC-Q100 5 Automotive (40C to +105C) AT PPAP submission 8D response time 1. Off-center parting line. Notes: 2. Available only on Revision G. 3. Available only on Revision L. 4. Some automotive parts are included in the product longevity program (PLP) and some are not, see www.micron.com/plp for a list of PLP parts. 5. Contact Micron for availability. Table 1: Key Timing Parameters CL = CAS (READ) latency Clock t t t t Speed Grade Frequency (MHz) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) -6 167 3-3-3 18 18 18 -6A 167 3-3-3 18 18 18 -7 143 3-3-3 15 15 15 PDF: 09005aef84ee4811 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 128mb x32 ait-aat sdram.pdf - Rev. C 4/16 EN 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.128Mb: x32 Automotive SDRAM Features Table 2: Address Table Parameter 4 Meg x 32 Configuration 1 Meg x 32 x 4 banks Refresh count 4K Row addressing 4K A 11:0 Bank addressing 4 BA 1:0 Column addressing 256 A 7:0 Table 3: 128Mb (x32) SDR Part Numbering Part Numbers Architecture MT48LC4M32B2TG 4 Meg x 32 MT48LC4M32B2P 4 Meg x 32 1 MT48LC4M32B2F5 4 Meg x 32 1 MT48LC4M32B2B5 4 Meg x 32 Note: 1. FBGA Device Decoder: www.micron.com/decoder. PDF: 09005aef84ee4811 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 128mb x32 ait-aat sdram.pdf - Rev. C 4/16 EN 2012 Micron Technology, Inc. All rights reserved.