AS4C64M8D2-25BAN Revision History 512Mb Auto-AS4C64M8D2 - 25BAN 60 ball FBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet Mar. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/63 - Rev.1.0 Mar. 2016AS4C64M8D2-25BAN Overview Features JEDEC Standard Compliant The 512Mb DDR2 is a high-speed CMOS Double- Data-Rate-Two (DDR2), synchronous dynamic random - JEDEC standard 1.8V I/O (SSTL 18-compatible) access memory (SDRAM) containing 512 Mbits in a 8-bit Power supplies: V & V = +1.8V 0.1V DD DDQ wide data I/Os. It is internally configured as a quad bank AEC-Q100 Compliant DRAM, 4 banks x 16Mb addresses x 8 I/Os. Automotive Temperature: TC = -40C ~105C All of the control and address inputs are synchronized with Supports JEDEC clock jitter specification a pair of externally supplied differential clocks. Inputs are Fully synchronous operation latched at the cross point of differential clocks (CK rising and Fast clock rate: 400 MHz CK falling). All I/Os are synchronized with a pair of Differential Clock, CK & CK bidirectional strobes (DQS and DQS ) in a source synchronous fashion. The address bus is used to convey Bidirectional single/differential data strobe row, column, and bank address information in RAS , 4 internal banks for concurrent operation CAS multiplexing style. Accesses begin with the 4-bit prefetch architecture registration of a Bank Activate command, and then it is Internal pipeline architecture followed by a Read or Write command. Read and write Precharge & active power down accesses to the DDR2 SDRAM are 4 or 8-bit burst Programmable Mode & Extended Mode registers oriented accesses start at a selected location and Posted CAS additive latency (AL): 0, 1, 2, 3, 4, 5 continue for a programmed number of locations in a WRITE latency = READ latency - 1 t programmed sequence. Operating the four memory CK banks in an interleaved fashion allows random access Burst lengths: 4 or 8 operation to occur at a higher rate than is possible with Burst type: Sequential / Interleave standard DRAMs. An auto precharge function may be DLL enable/disable enabled to provide a self-timed row precharge that is Off-Chip Driver (OCD) initiated at the end of the burst sequence. A sequential and - Impedance Adjustment gapless data rate is possible depending on burst length, - Adjustable data-output drive strength CAS latency, and speed grade of the device. On-die termination (ODT) The device is designed to comply with DDR2 DRAM RoHS compliant key features such as posted CAS with additive latency, Auto Refresh and Self Refresh Write latency = Read latency -1, Off-Chip Driver (OCD) 8192 refresh cycles / 64ms impedance adjustment, and On Die Termination(ODT). - Average refresh period 7.8s -40C TC +85 C 3.9s +85C TC +105C 60-ball 8 x 10 x 1.2mm (max) FBGA package - Pb and Halogen Free Table 1. Ordering Information Part Number Org Temperature MaxClock (MHz) Package Automotive 64Mx8 400 60-ball FBGA AS4C64M8D2-25BAN -40C to 105C Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR2-800 400MHz 5 12.5 12.5 Confidential - 2/63 - Rev.1.0 Mar. 2016