8Gb: x16, x32 GDDR5 SGRAM Features GDDR5 SGRAM MT51J256M32 16 Meg x 32 I/O x 16 banks, 32 Meg x 16 I/O x 16 banks Address training: Address input monitoring via DQ Features pins V = V = 1.5V 3% and 1.35V 3% DD DDQ WCK2CK clock training: Phase information via EDC Data rate: 6.0 Gb/s, 7.0 Gb/s, 8.0 Gb/s pins 16 internal banks Data read and write training via read FIFO (FIFO t t Four bank groups for CCDL = 3 CK depth = 6) 8n-bit prefetch architecture: 256-bit per array read Read FIFO pattern preloaded by LDFF command or write access for x32 128-bit for x16 Direct write data load to read FIFO by WRTR com- Burst length (BL): 8 only mand Programmable CAS latency: 724 Consecutive read of read FIFO by RDTR command Programmable WRITE latency: 47 Read/write data transmission integrity secured by Programmable CRC READ latency: 23 cyclic redundancy check (CRC-8) Programmable CRC WRITE latency: 814 Read/write EDC on/off mode Programmable EDC hold pattern for CDR Low power modes Precharge: Auto option for each burst access RDQS mode on EDC pin Auto refresh and self refresh modes On-die temperature sensor with readout Refresh cycles: 16,384 cycles/32ms Automatic temperature sensor controlled self Interface: Pseudo open drain (POD-15) compatible refresh rate outputs: 40 pull-down, 60 pull-up Vendor ID, FIFO depth and density info fields for On-die termination (ODT): 60 or 120 (NOM) identification ODT and output driver strength auto calibration Mirror function with MF pin with external resistor ZQ pin: 120 Boundary scan function with SEN pin Programmable termination and driver strength off- Lead-free (RoHS-compliant) and halogen-free sets packaging Selectable external or internal V for data inputs REF T = 0C to +95C C programmable offsets for internal V REF Separate external V for address/command 1 REF Options Marking inputs Organization x32/x16 mode configuration set at power-up with 256 Meg x 32 (words x bits) 256M32 EDC pin FBGA package Single-ended interface for data, address, and 170-ball (12mm x 14mm) HF command Timing maximum data rate Quarter data rate differential clock inputs CK t, 6.0 Gb/s, 5.0 Gb/s -60 CK c for address and commands 7.0 Gb/s, 6.0 Gb/s -70 Two half data rate differential clock inputs, WCK t 8.0 Gb/s, 6.0 Gb/s -80 and WCK c, each associated with two data bytes Operating temperature (DQ, DBI n, EDC) Commercial (0C T +95C) None C DDR data (WCK) and addressing (CK) Revision A SDR command (CK) Write data mask function via address bus (single/ 1. Not all options listed can be combined to Note: double byte mask) define an offered product. Use the part Data bus inversion (DBI) and address bus inversion catalog search on 8Gb: x16, x32 GDDR5 SGRAM Features Figure 1: Part Numbering MT51J 256M32 HF -80 : A Micron Memory Revision A Configuration Temperature 256M32 = 256 Meg x 32 : = Commercial Package Data Rate HF = 170-ball 12.00mm x 14.00mm FBGA -80 = 8.0 Gb/s -70 = 7.0 Gb/s -60 = 6.0 Gb/s Note: 1. This Micron GDDR5 SGRAM is available in different speed bins. The operating range and AC timings of a faster speed bin are a superset of all slower speed bins. Therefore it is safe to use a faster bin device as a drop-in replacement of a slower bin device when operated within the supply voltage and frequency range of the slower bin device. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Microns web site: