128MB, 256MB, 512MB (x72, ECC, SR), PC3200 184-Pin DDR SDRAM UDIMM MT9VDDT1672A 128MB DDR SDRAM MT9VDDT3272A 256MB MT9VDDT6472A 512MB UNBUFFERED DIMM For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features Figure 1: 184-Pin DIMM (MO-206) JEDEC-standard 184-pin dual in-line memory Standard 1.25in. (31.75mm) module (DIMM) Fast data transfer rate: PC3200 CAS Latency 3 Utilizes 400 MT/s DDR SDRAM components Supports ECC error detection and correction 128MB (16 Meg x 72), 256MB (32 Meg x 72), 512MB (64 Meg x 72) VDD= VDDQ= +2.6V VDDSPD = +2.3V to +3.6V +2.6V I/O (SSTL 2 compatible) Commands entered on each positive CK edge OPTIONS MARKING DQS edge-aligned with data for READs center- Package aligned with data for WRITEs 184-pin DIMM (standard) G Internal, pipelined double data rate (DDR) 184-pin DIMM (lead-free) Y architecture two data accesses per clock cycle Frequency/CAS Latency Bidirectional data strobe (DQS) transmitted/ received with datai.e., source-synchronous data 5ns, 400 MT/s (200 MHz), CL = 3 -40B capture PCB Differential clock inputs (CK and CK ) 1.25in. (31.75mm) None Four internal device banks for concurrent operation Programmable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6s (128MB), 7.8125s (256MB, 512MB) maximum average periodic refresh interval Serial Presence-Detect (SPD) with EEPROM Programmable READ CAS latency Gold edge contacts Table 1: Address Table 128MB 256MB 512MB 4K 8K 8K Refresh Count Row Addressing 4K (A0A11) 8K (A0A12) 8K (A0A12) Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Device Configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1K (A0A9) 1K (A0A9) 2K (A0A9, A11) Column Addressing 1 (S0 ) 1 (S0 ) 1 (S0 ) Module Rank Addressing pdf: 09005aef80a43e7d, source: 09005aef80a43d77 DDA9C16 32 64x72AG.fm - Rev. B 9/04 EN 1 2004 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB, 256MB, 512MB (x72, ECC, SR), PC3200 184-Pin DDR SDRAM UDIMM Table 2: Part Numbers and Timing Parameters LATENCY PART NUMBER MODULE CONFIGURATION MODULE MEMORY CLOCK/ t t DENSITY BANDWIDTH DATA RATE (CL - RCD - RP) MT9VDDT1672AG-40B 128MB 16 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3 MT9VDDT1672AY-40B 128MB 16 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3 256MB 32 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3 MT9VDDT3272AG-40B MT9VDDT3272AY-40B 256MB 32 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3 MT9VDDT6472AG-40B 512MB 64 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3 MT9VDDT6472AY-40B 512MB 64 Meg x 72 3.2 GB/s 5ns/400 MT/s 3-3-3 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9VDDT3272AG-40BA1. pdf: 09005aef80a43e7d, source: 09005aef80a43d77 Micron Technology, Inc., reserves the right to change products or specifications without notice. DDA9C16 32 64x72AG.fm - Rev. B 9/04 EN 2 2004 Micron Technology, Inc.