74ABT125D Nexperia

74ABT125 Quad buffer 3-state Rev. 6 3 November 2011 Product data sheet 1. General description The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT125 device is a quad buffer that is ideal for driving bus lines. The device features four Output Enables (1OE, 2OE, 3OE, 4OE), each controlling one of the 3-state outputs. 2. Features and benefits Quad bus interface 3-state buffers Live insertion and extraction permitted Output capability: HIGH 32 mA LOW +64 mA Power-up 3-state Inputs are disabled during 3-state mode Latch-up protection exceeds 500 mA per JESD78 class II level A ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT125N 40 C to +85 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74ABT125D 40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74ABT125DB 40 C to +85 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74ABT125PW 40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74ABT125BQ 40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm74ABT125 NXP Semiconductors Quad buffer 3-state 4. Functional diagram 2 1A 1Y 3 2 1 3 1 1OE 1 EN1 2A 2Y 6 5 5 6 nY 4 nA 2OE 4 9 3A 3Y 9 8 8 nOE 10 mna227 10 3OE 12 12 4A 4Y 11 11 13 13 4OE mna229 mna228 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 5. Pinning information 5.1 Pinning 74ABT125 terminal 1 74ABT125 index area 1OE 1 14 V CC 1A 2 13 4OE 1A 2 13 4OE 1Y 3 12 4A 1Y 3 12 4A 4 11 2OE 4Y 2OE 4 11 4Y 2A 5 (1) 10 3OE 2A 5 10 3OE GND 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y 001aai027 001aai028 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 74ABT125 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 3 November 2011 2 of 16 7 1 GND 1OE 3Y 8 14 V CC