74AHC04D-Q100J Nexperia

74AHC04-Q100 74AHCT04-Q100 Hex inverter Rev. 2 10 September 2020 Product data sheet 1. General description The 74AHC04-Q100 74AHCT04-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC04-Q100 74AHCT04-Q100 provides six inverting buffers. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Balanced propagation delays Inputs accept voltages higher than V CC Input levels: For 74AHC04-Q100: CMOS level For 74AHCT04-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC04D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT04D-Q100 74AHC04PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package SOT402-1 14 leads body width 4.4 mm 74AHCT04PW-Q100 74AHC04BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package 74AHCT04BQ-Q100 no leads 14 terminals body 2.5 3 0.85 mmNexperia 74AHC04-Q100 74AHCT04-Q100 Hex inverter 4. Functional diagram 1 1 2 1A 1Y 2 1 1 3 4 3 2A 2Y 4 1 5 6 5 3A 3Y 6 1 9 8 4Y 9 4A 8 1 5Y 11 5A 10 11 10 13 6A 6Y 12 1 13 12 mna342 mna343 Fig. 1. Logic symbol Fig. 2. IEC logic symbol A Y mna341 Fig. 3. Logic diagram (one inverter) 5. Pinning information 5.1. Pinning 74HC04 74HCT04 terminal 1 index area 1Y 2 13 6A 3 12 2A 6Y 74HC04 74HCT04 2Y 4 11 5A 3A 5 10 5Y (1) GND 1A 1 14 V CC 3Y 6 9 4A 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 001aac442 3A 5 10 5Y Transparent top view 3Y 6 9 4A (1) This is not a ground pin. There is no electrical or GND 7 8 4Y mechanical requirement to solder the pad. In case 001aac441 soldered, the solder land should remain floating or connected to GND Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74AHC AHCT04 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 10 September 2020 2 / 13 GND 7 1 1A 4Y 8 14 V CC