74AHC1G4212GW-Q10H Nexperia

74AHC1G4212-Q100 12-stage divider and oscillator Rev. 3 13 January 2022 Product data sheet 1. General description 74AHC1G4212-Q100 is a 12-stage divider and oscillator. It consists of a chain of 12 flip-flops. Each flip-flop divides the frequency of the previous flip-flop by two, consequently the 12 74AHC1G4212-Q100 counts up to 2 = 4096. The single inverting stage (X1 to X2) functions as a crystal oscillator or an input buffer for an external oscillator. When used as a buffer the output X2 should be left floating. The frequency of the output (Q) is the frequency applied to X1 divided by 4096. The divider advances on the negative-going transition of X1. The X1 input is overvoltage tolerant. This feature allows the use of this device as a voltage level translator in mixed voltage environments. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F: exceeds 2000 V CDM JESD22-C101E: exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC1G4212GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mm 4. Marking Table 2. Marking codes Type number Marking 1 74AHC1G4212GW-Q100 C2 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code.Nexperia 74AHC1G4212-Q100 12-stage divider and oscillator 5. Functional diagram X2 FF1 FF2 FF12 X1 Q 1 4 D D D 12-STAGE CP CP CP X1 COUNTER X2 2 Q1 Q2 Q10 Q aaa-022708 aaa-022707 Fig. 2. Logic diagram Fig. 1. Logic symbol 6. Pinning information 6.1. Pinning 74AHC1G4212 X1 1 5 V CC X2 2 3 4 GND Q aaa-022709 Fig. 3. Pin configuration SOT353-1 (TSSOP5) 6.2. Pin description Table 3. Pin description Symbol Pin Description X1 1 clock input/oscillator pin X2 2 oscillator pin GND 3 ground (0 V) Q 4 divider output V 5 supply voltage CC 7. Functional description 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 12288 X1 Q aaa-022711 Fig. 4. Timing diagram 74AHC1G4212 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 3 13 January 2022 2 / 11