74AHCT125PW-Q100,1 Nexperia

74AHC125-Q100 74AHCT125-Q100 Quad buffer/line driver 3-state Rev. 2 12 June 2020 Product data sheet 1. General description The 74AHC125-Q100 74AHCT125-Q100 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Balanced propagation delays All inputs have a Schmitt-trigger action Input levels: For 74AHC125-Q100: CMOS level For 74AHCT125-Q100: TTL level ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC125D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT125D-Q100 74AHC125PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package SOT402-1 14 leads body width 4.4 mm 74AHCT125PW-Q100 74AHC125BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74AHCT125BQ-Q100 14 terminals body 2.5 3 0.85 mmNexperia 74AHC125-Q100 74AHCT125-Q100 Quad buffer/line driver 3-state 4. Functional diagram 2 1A 1Y 3 2 1 1 1OE 3 1 EN1 5 2A 2Y 6 5 4 2OE 6 4 9 3A 3Y 8 9 8 3OE 10 10 4A 4Y nA nY 12 11 12 11 4OE 13 13 nOE mna228 mna229 mna227 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one buffer) 5. Pinning information 5.1. Pinning 74AHC125 74AHCT125 terminal 1 index area 1A 2 13 4OE 1Y 3 12 4A 74AHC125 74AHCT125 4 11 2OE 4Y (1) 2A 5 10 3OE GND 1 14 1OE V CC 2Y 6 9 3A 1A 2 13 4OE 1Y 3 12 4A 4 11 2OE 4Y 001aah082 2A 5 10 3OE Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or 7 GND 8 3Y mechanical requirement to solder the pad. In case 001aae755 soldered, the solder land should remain floating or connected to GND Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74AHC AHCT125 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 12 June 2020 2 / 15 GND 7 1 1OE 3Y 8 14 V CC