74AHCT240D-Q100J Nexperia

74AHCT240-Q100 Octal buffer/line driver inverting 3-state Rev. 3 29 June 2020 Product data sheet 1. General description The 74AHCT240-Q100 is an 8-bit inverting buffer/line drivers with 3-state outputs. This device can be used as two 4-bit buffers or one 8-bit buffer. It features two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are over voltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accept voltages higher than V CC 74AHCT240-Q100 operates with TTL input levels ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHCT240D-Q100 -40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74AHCT240PW-Q100 -40 C to +125 C TSSOP20 plastic thin shrink small outline package SOT360-1 20 leads body width 4.4 mm 74AHCT240BQ-Q100 -40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal SOT764-1 enhanced very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mmNexperia 74AHCT240-Q100 Octal buffer/line driver inverting 3-state 4. Functional diagram 1 EN 2 18 16 4 2 1A0 1Y0 18 14 6 3 17 2A0 2Y0 8 12 4 1A1 1Y1 16 15 2A1 5 2Y1 19 EN 6 1A2 1Y2 14 13 2A2 2Y2 7 11 9 8 1Y3 12 1A3 13 7 9 11 2A3 2Y3 15 5 17 3 1 1OE 19 2OE mgu779 mgu778 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74AHCT240-Q100 terminal 1 index area 1A0 2 19 2OE 2Y0 3 18 1Y0 4 17 1A1 2A0 74AHCT240-Q100 2Y1 5 16 1Y1 1OE 1 20 V 1A2 6 15 2A1 CC 1A0 2 19 2OE 2Y2 7 14 1Y2 2Y0 3 18 1Y0 (1) 1A3 8 13 2A2 GND 1A1 4 17 2A0 9 12 2Y3 1Y3 2Y1 5 16 1Y1 1A2 6 15 2A1 aaa-009410 2Y2 7 14 1Y2 1A3 8 13 2A2 Transparent top view 2Y3 9 12 1Y3 (1) This is not a ground pin. There is no electrical or GND 10 11 2A3 mechanical requirement to solder the pad. In case aaa-009409 soldered, the solder land should remain floating or connected to GND. Fig. 3. Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20) Fig. 4. Pin configuration SOT764-1 (DHVQFN20) 74AHCT240 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 29 June 2020 2 / 13 GND 10 1 1OE 2A3 11 20 V CC