74ALVC125PW,112 Nexperia

74ALVC125 Quad buffer/line driver 3-state Rev. 4 30 April 2021 Product data sheet 1. General description The 74ALVC125 is a quad non-inverting buffer/line driver with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH on the nOE pin causes the outputs to assume a high-impedance OFF-state. 2. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B (2.7 V to 3.6 V) ESD protection: MM JESD22-A115-A exceeds 200 V HBM JESD22-A114E exceeds 2000 V Multiple package options Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC125D -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74ALVC125PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74ALVC125BQ -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74ALVC125 Quad buffer/line driver 3-state 4. Functional diagram 2 1A 1Y 3 2 1 1 1OE 3 1 EN1 5 2A 2Y 6 5 4 2OE 6 4 9 3A 3Y 8 9 8 3OE 10 10 4A 4Y 12 11 12 11 4OE 13 13 mna228 mna229 Fig. 1. Logic symbol Fig. 2. IEC logic symbol nA nY nOE mna227 Fig. 3. Logic diagram (one buffer) 5. Pinning information 5.1. Pinning 74ALVC125 terminal 1 index area 2 13 1A 4OE 1Y 3 12 4A 74ALVC125 2OE 4 11 4Y 2A 5 (1) 10 3OE GND 1 14 1OE V CC 2Y 6 9 3A 2 13 1A 4OE 3 12 1Y 4A 4 11 2OE 4Y 001aah090 5 10 2A 3OE Transparent top view 6 2Y 9 3A (1) This is not a ground pin. There is no electrical or 7 GND 8 3Y mechanical requirement to solder the pad. In case 001aah089 soldered, the solder land should remain floating or connected to GND Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74ALVC125 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 30 April 2021 2 / 13 GND 7 1 1OE 3Y 8 14 V CC