74ALVC164245-Q100 16-bit dual supply translating transceiver 3-state Rev. 4 27 July 2021 Product data sheet 1. General description The 74ALVC164245-Q100 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74ALVC164245-Q100 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are referenced to V and pins nBn are referenced to V . CC(A) CC(B) In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The nAn outputs must be set 3-state and the voltage on the A-bus must be smaller than V (typical 0.7 V). V V (except in suspend mode). diode CC(B) CC(A) This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range: 3 V port (V ): 1.5 V to 3.6 V CC(A) 5 V port (V ): 1.5 V to 5.5 V CC(B) CMOS low power consumption Overvoltage tolerant inputs to 5.5 V Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Control inputs voltage range from 2.7 V to 5.5 V High-impedance outputs when V or V = 0 V CC(A) CC(B) Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )Nexperia 74ALVC164245-Q100 16-bit dual supply translating transceiver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC164245DGG-Q100 -40 C to +125 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mm 4. Functional diagram 2DIR 1DIR 1OE 2OE 2A0 1A0 1B0 2B0 1A1 2A1 1B1 2B1 1A2 2A2 1B2 2B2 1A3 2A3 1B3 2B3 1A4 2A4 1B4 2B4 1A5 2A5 1B5 2B5 1A6 2A6 1B6 2B6 1A7 2A7 1B7 2B7 001aaa789 Fig. 1. Logic symbol 74ALVC164245 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 27 July 2021 2 / 14